Li-bo Cheng, F. Anghinolfi, Ke Wang, Hong-Bo Zhu, W. Lu, Zhen-an Liu
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引用次数: 3
Abstract
As physicists want to put more and more functionalities and algorithms into frontend ASICs, the logic design (of some ASICs) become more and more complicated. A reliable, robust functional verification testbench is one of the most important part during ASIC design. This paper presents a well-constructed testbench based on Universal Verification Methodology(UVM) research for ATLAS Phase-II upgrade silicon strip detector front-end readout chip.
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