{"title":"A linear threshold gate implementation in single electron technology","authors":"C. Lageweg, S. Cotofana, S. Vassiliadis","doi":"10.1109/IWV.2001.923145","DOIUrl":null,"url":null,"abstract":"In this paper we focus on the design of threshold logic functions in Single Electron Tunneling (SET) technology, using the tunnel junction's specific behavior i.e., the ability to control the transport of individual electrons. We introduce a novel design of an n-input linear threshold gate which can accommodate both positive and negative weights and built-in signal amplification, using 1 tunnel junction and n+2 true capacitors. As an example we present a 4-input threshold gate with both positive and negative weights.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"116","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWV.2001.923145","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 116
Abstract
In this paper we focus on the design of threshold logic functions in Single Electron Tunneling (SET) technology, using the tunnel junction's specific behavior i.e., the ability to control the transport of individual electrons. We introduce a novel design of an n-input linear threshold gate which can accommodate both positive and negative weights and built-in signal amplification, using 1 tunnel junction and n+2 true capacitors. As an example we present a 4-input threshold gate with both positive and negative weights.