A Proposed Design of Conventional 4-Bit Carry Look-Ahead Adder Improving Performance

Abstract

This paper presents a method towards the improved performance parameters of conventional CMOS based 4-bit carry look-ahead adder. Conventional CLA adder has high numbers of transistors and high input impedance due to which various performance aspects are affected. Due to high input impedance, its delay and power consumption are high. Therefore, to increase the performance and to reduce delay, we have proposed an advanced version of CLA adder where hybrid logic based XOR gate and GDI AND gates have been used as input to reduce the transistor count as well as to improve performance. Finally, performance of modified adder has been compared with the conventional CLA adder. We have noticed that modified CLA adder showed better performance than the conventional CLA adder. Simulation has been done with Cadence virtuoso 90nm technology.