Full Adder Circuit using Multi-Input MRL

Suparlerk Yamtim, S. Tooprakai
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引用次数: 1

Abstract

this paper proposes the Full Adder Circuit using Multi-Input MRL without CMOS. It is designed by Multi-Input MRL which component and delay time less than 1-bit full adder circuit using Hybrid Memristor-CMOS logic. Structure of Purpose circuit is most simple. The performances of Purpose circuit are compared with another full adder circuits are carried out by using LTspice simulator
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使用多输入MRL的全加法器电路
本文提出了一种不含CMOS的多输入MRL全加法器电路。采用混合忆阻器- cmos逻辑,采用多输入MRL设计元件和延迟时间小于1位的全加法器电路。目的电路结构最简单。利用LTspice模拟器对目的电路与其他全加法器电路的性能进行了比较
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