HLS Based Implementation of Modified DE-RIW Algorithm on FPGA and P-SoC

Abstract

Being lossless, Reversible Image Watermarking (RIW) with Difference Expansion (DE) algorithm is crucial for content authentication, especially for high security medical and military images. In DE-RIW, the secret data bit can be embedded into the Least Significant Bit (LSB) of the difference between two neighboring pixels. Very few researchers have worked on High Level Synthesis (HLS) based implementation of its modified algorithm on Field Programmable Gate Array (FPGA) and Programmable System-On-Chip (P-SoC). Here, to get accelerated performance a modified DE-RIW algorithm is proposed along with its VLSI based hardware implementation both on Xilinx FPGA and P-SoC. In the proposed approach, scheduling is done considering resource constraint criteria. Implementation results through simulation up to burning the design on board needs fewer resources (adder, subtractor, multiplier, divider, register, multiplexer, and comparator) as compared with the similar existing architectures in the literature based on RIW.