The new low power 10-bit pipelined ADC using novel background calibration technique

Abstract

The paper deals with new background calibration technique, which is utilized in new 10-bit low power pipelined ADC. The switched-capacitor approach is used in designed ADC as well. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches, the fully differential circuitry was utilized. The operational transconductance amplifier (OTA) was used in design instead of op-amp. The power consumption of the OTA and other analog parts were taken into account in design procedure. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.