A CMOS Analog Frontend for a Passive UHF RFID Tag

A. Facen, A. Boni
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引用次数: 34

Abstract

The paper discusses the design of the analog frontend of a passive UHF RFID tag, compatible with ISO/IEC 18000-6b standard. An efficient ESD-protected power retrieving circuit, based on the antenna features, a rectifier bridge and a charge pump, is introduced, as well as an auto-calibrated clock generator. The chip, implemented in a 0.18mum digital CMOS technology, does not need any post-fabrication trimming or external component besides the antenna; according to simulations, a correct communication is achieved at a distance of several meters between reader and tag
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无源超高频RFID标签的CMOS模拟前端
本文讨论了一种符合ISO/IEC 18000-6b标准的无源超高频RFID标签的模拟前端设计。根据天线的特点,设计了一种高效的防静电功率回收电路,包括整流桥和电荷泵,以及自动校准时钟发生器。该芯片采用0.18 μ m数字CMOS技术实现,除了天线外,不需要任何后期修整或外部组件;仿真结果表明,阅读器与标签之间在几米的距离上实现了正确的通信
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