Design of Baseband Analog with Filter Tuning for 5.8GHz DSRC Transceiver in ETCS

Ji Hoon Song, Kangyoon Lee
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引用次数: 1

Abstract

This paper introduces a design of baseband analog with high performance IRR (Image Rejection Ratio) to using wide-bandwidth for DSRC (Dedicated Short Range Communication) transceiver. In addition, an automatic filter tuning system has applied to in this circuit for higher PVT tolerance and accuracy of bandwidth. To reduce adjacent interferers and image signal in baseband circuit, Complex Band Pass Filter (BPF) is used in this system. Baseband analog has high performance of IRR 66.5 dB at 3-dB bandwidth and the Intermediate Frequency (IF) are 10MHz. This circuit is designed in 130nm CMOS process. Power consumption is 7.46mW under 1.2V power supply.
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ETCS中5.8GHz DSRC收发器带滤波器调谐基带模拟设计
本文介绍了一种具有高性能IRR(图像抑制比)的基带模拟电路的设计,以充分利用DSRC(专用短距离通信)收发器的带宽。此外,该电路还采用了自动滤波调谐系统,以提高PVT公差和带宽精度。为了减少基带电路中的相邻干扰和图像信号,该系统采用了复合带通滤波器(BPF)。基带模拟在3db带宽下的IRR为66.5 dB,中频为10MHz。该电路采用130nm CMOS工艺设计。1.2V电源下的功耗为7.46mW。
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