Design of Low Power & High Speed Comparator of SAR ADC using 180nm Technology

Abstract

Low power and high-speed comparator design are presented in this article. Design is intended for the implementation of SAR ADC. The advantage of the proposed design can minimize power dissipation and maximize speed in SAR ADC. Simulation results are obtained in 0.18um Technology in the cadence tool. This design exhibit improved accuracy and less power consumption about 129.8$\mu \mathrm{W}$ with sampling frequency 100MHz and 1.8V supply. Prior work done is compared with simulated results and progress is also marked in present work.