An efficient and cost-effective context-parsing architecture for dynamically reconfigurable cryptographic processor

Abstract

A dynamically reconfigurable cryptographic processor (DRCP), which are driven by configuration context, has been proven to be efficient and cost-effective in the block cryptography domains. Two techniques focused on optimizing the context-parsing organization and the context memory are proposed: 1) The classification-based multi-concurrent configuration (CMC) can obviously reduce the parsing time cost and configuration delay. 2) The diversified context-abstraction compression (DCC) provides three different ways to compress the context memory and ease the context access based on data flow graph (DFG) abstraction. The related processor and architecture are implemented with TSMC 65nm technology. And the design achieves the context memory for block cipher algorithms reduced to less than 40%, while the CMC and DCC can also help to choose a most efficient way to compress the context.