Optimizing FPGAs for supporting WBANs

Abstract

The usage of Field Programmable Gate Arrays (FPGAs) in resource-constrained devices depends on energy consumption optimization techniques. Existing techniques to reduce FPGA's energy consumption have been based on several levels of abstraction, from new transistor technologies to mapping algorithms present in circuit CAD tools. This work proposes a bio-inspired technique, called AntES (plAcement, pipeliNing and reTiming for Energy Saving), that integrates the FPGA CAD flow joining placement, pipelining and retiming steps in order to reduce energy consumption and support WBANs.