A model-driven validation & verification environment for embedded systems

A. Gargantini, E. Riccobene, P. Scandurra
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引用次数: 8

Abstract

This paper presents a validation and verification tool component, based on the abstract state machine formal method, that we are developing to support high level formal analysis of embedded system model-driven design. This component is integrated into a model-driven environment for HW/SW co-design that provides a graphical high-level representation of HW and SW components by means of UML profiles for SystemC/multi-thread C, and allows C/C++/SystemC code generation/back-annotation from/to graphical UML models.
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用于嵌入式系统的模型驱动验证和验证环境
本文提出了一个基于抽象状态机形式化方法的验证和验证工具组件,以支持嵌入式系统模型驱动设计的高级形式化分析。该组件被集成到一个模型驱动的环境中,用于HW/SW协同设计,该环境通过SystemC/多线程C的UML概要文件提供了HW和SW组件的图形高级表示,并允许C/ c++ /SystemC代码生成/从/到图形UML模型的反向注释。
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