A 28.8 Mb/s 4/spl times/4 MIMO 3G high-speed downlink packet access receiver with normalized least mean square equalization

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332773

D. Garrett, G. Woodward, L. Davis, G. Knagge, C. Nicol

引用次数: 22

Abstract

A receiver for high-speed downlink packet access supporting 28.8 Mb/s using QPSK over a 5 MHz frequency selective 4/spl times/4 MIMO wireless channel (5.76 b/s/Hz). A key feature is the normalized least mean squares space-time equalizer using a pilot correlator for more accurate adaptation. Fabricated in 0.18 /spl mu/m 6M CMOS, the core of the chip covers an 11.6 mm/sup 2/ area.

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具有归一化最小均方均衡的28.8 Mb/s 4/spl times/4 MIMO 3G高速下行分组接入接收机

一种用于高速下行分组访问的接收器，支持28.8 Mb/s，使用QPSK在5 MHz频率选择4/spl倍/4 MIMO无线信道(5.76 b/s/Hz)。一个关键的特点是标准化的最小均方时空均衡器使用导频相关器更准确的适应。该芯片采用0.18 /spl mu/m的6M CMOS工艺，核心面积为11.6 mm/sup / m2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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