Fault-intolerance of reconfigurable systolic arrays

Abstract

Identification, characterization, and construction of fault patterns that are catastrophic for linear systolic arrays are discussed. It is shown that for a given link configuration in the array, it is possible to identify all PE (processing element) catastrophic fault patterns. The requirement on the minimum number of faults in a fault pattern and its spectrum (spread out) for it to be catastrophic is shown to be a function of the length of the longest bypass link available, and not of the total number of bypass links. The paper also gives bounds on the width of a catastrophic fault spectrum.<>