Design of delay-insensitive three dimension pipeline array multiplier for image processing

Abstract

This paper presents a novel delay-insensitive three dimension pipeline array multiplier. The organization combines deep (gate-level) pipelining of Manchester adders with a two dimensional cross-pipeline mesh for multiplicand and multiplier propagation and partial product bits calculation. Fine grain pipelining with elimination of broadcasting and completion trees leads to high-throughput without use of dynamic logic that leaves the door open for further improvement of performance.