A single chip motion JPEG codec LSI

Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI:10.1109/CICC.1997.606619

S. Okada, Y. Matsuda, T. Watanabe, K. Kondo

引用次数: 1

Abstract

We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640/spl times/480) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI uses compression ratio control to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer so that it can process signals at high speed without using high-speed image memory. The JPEG codec core is small (40,000 gates) and power consumption is low (220 mW) for broader application in image processing in consumer markets.

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单片运动JPEG编解码LSI

我们已经开发了一种单芯片运动JPEG编解码器LSI，它可以压缩和解压vga大小(640/spl次/480)JPEG图像的速率为每秒30帧，只需连接一个外部缓冲存储器芯片。LSI在内存容量有限的情况下，通过压缩比控制来存储固定数量的图像，并对存储在帧缓冲区中的数据进行压缩，从而可以在不使用高速图像存储器的情况下高速处理信号。JPEG编解码器核心很小(40,000门)，功耗低(220兆瓦)，可在消费市场的图像处理中得到更广泛的应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of CICC 97 - Custom Integrated Circuits Conference

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