{"title":"Advanced Instruction Folding for an Object-oriented Processor","authors":"A. Fong, C. Yau, Yijun Liu","doi":"10.1109/ITNG.2013.136","DOIUrl":null,"url":null,"abstract":"jHISC is an object-oriented processor with RISC core and architectural support for object instructions. It is a three-addressing machine instead of a stack machine as JVM. With instruction folding techniques, several JVM operations could be translated into fewer or one jHISC three-address machine code, and they execute more effectively. This paper presents an improved folding algorithm for jHISC V4.0 in which the bytecodes are divided into six types and treat the intermediate operation result as P type operations and our instruction folding algorithm is further implemented in hardware level to further reduce the translation burden in software level.","PeriodicalId":320262,"journal":{"name":"2013 10th International Conference on Information Technology: New Generations","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 10th International Conference on Information Technology: New Generations","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITNG.2013.136","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
jHISC is an object-oriented processor with RISC core and architectural support for object instructions. It is a three-addressing machine instead of a stack machine as JVM. With instruction folding techniques, several JVM operations could be translated into fewer or one jHISC three-address machine code, and they execute more effectively. This paper presents an improved folding algorithm for jHISC V4.0 in which the bytecodes are divided into six types and treat the intermediate operation result as P type operations and our instruction folding algorithm is further implemented in hardware level to further reduce the translation burden in software level.
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