Network Model Compensation For Single-Point Measurements Of Multi-Pin Devices When Using Non-Invasive Current Estimation

Abstract

Power delivery network (PDN) model development is often simplified using superports or pin-groups for high pin count devices. This approach significantly reduces model complexity but can compromise accuracy in holistic time- and frequency-domain analyses. In the context of the non-invasive current estimation (NICE) technique for packaged, high-performance integrated circuits (ICs), this paper describes the limitations of using pin-group PDN models in distributed impedance applications. DC error calibration factors are calculated, and tuned AC error compensation networks are proposed. These fundamental techniques for working with overly simplified models in highly distributed power integrity applications are derived and demonstrated through simulation and measurement on exemplar hardware.