An embedded FPGA architecture for efficient visual saliency based object recognition implementation

Abstract

In this article, we propose a new optimized embedded architecture based soft-core processors oriented to visual attention based object recognition applications. Our recognition approach relies mainly on two specific modules for online processing of acquired images in real-time: a novel saliency based feature detector/descriptor module and then an object classifier module. To deal with such parallel/pipeline image processing tasks, we have designed a new multistage architecture, which is implementing on FPGA chip leading ultimately to a faster prototyping of this proposed architecture without ASIC (Application Specific Integrated Circuit) related problems. the resulting FPGA implementations demonstrate that the proposed homogeneous pipelined systems achieve significant speedups compared to the original serial implementation and delivers a high reduction of the memory and FPGA resource utilization on an image of 256 × 256 pixels at up to 100 frames/s.