Multi-threaded vectorization

Abstract

A new architectural concept called multithreaded vecrorization is introduced to bmaden the range of “vectorizable” code while keeping the same pipeline efficiency and simplicity as in conventional vector machines. This architecture can be viewed as a compromise between vector and VLIW machines. A compiler algorithm based on the software. pipelining technique is proposed to map loops to multi-threaded architecture. For several conventionally considered nonvectorizable kernels, we show this architecture can deliver as much as 60 percent of performance gain over conventional vector machines.