Exploring the Suitability of Stacking Devices in a Vertical Nanowire to Implement a CMOS Inverter

Abstract

Stacking devices in a 3D configuration by using a vertical topology is considered as the next step to improve electronic devices and circuits performance. For instance, a CMOS inverted can be built by continuously depositing both inter-metal and metal layers. This new IC manufacturing proposal has been simulated by using Sentaurus 3D TCAD software. We have analyzed the influence of different device design parameters to optimize its performance. Finally, we have also explored the feasibility to implement a 5-stage ring oscillator circuit by using the proposed stack.