Design and Analysis of 3D Integrated Folded Ferro-Capacitive Crossbar Array (FC²A) for Brain-Inspired Computing System

IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2024-07-22 DOI:10.1109/JETCAS.2024.3432458
Sherin A. Thomas;Suyash Kushwaha;Rohit Sharma;Devarshi Mrinal Das
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Abstract

This paper presents a novel 3D folded capacitive synaptic crossbar array designed for in-memory computing architectures. In this architecture, the bitline is folded over the wordline to enhance the synaptic density. The proposed folded capacitive crossbar array ( $FC^{2}A$ ) architecture decreases the wordline interconnect length and physical crossbar area by 50%. Thus, it helps to reduce the crossbar-associated parasitics and optimize space utilization. The proposed folded capacitive synaptic crossbar is used for designing a brain-inspired computing system (BiCoS) to recognize different patterns using CMOS technology. The BiCoS systems are prone to various reliability issues caused by the crossbar’s parasitics. Hence, the 3D folded capacitive crossbar’s Q3D model is developed to investigate the crossbar-associated parasitics and its effect on the proposed system is analyzed. The impact of crossbar parasitics is investigated for two cases: Firstly, how the three different spiking patterns (regular spiking, fast-spiking, and chattering) of the Izhikevich neuron change for the different crossbar sizes. Secondly, the impact is analyzed on the pattern recognition rate, which gets reduced to 70%. Addressing these challenges is critical to ensure the correct and robust working of the proposed system. Therefore, we propose a solution to effectively overcome and resolve these adverse effects. The energy consumed to recognize each pattern is calculated, and the average energy needed is $0.25\,nJ$ , which is significantly less when compared to the other state-of-the-art works. The circuit is implemented using 65nm standard CMOS technology.
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用于脑启发计算系统的三维集成折叠式铁电容横杆阵列(FC 2 A)的设计与分析
本文介绍了一种专为内存计算架构设计的新型三维折叠电容式突触横杆阵列。在该架构中,位线折叠在字线上,以提高突触密度。所提出的折叠电容式交叉条阵列($FC^{2}A$)架构可将字线互连长度和物理交叉条面积减少 50%。因此,它有助于减少与横梁相关的寄生效应,优化空间利用率。所提出的折叠式电容突触横杆可用于设计大脑启发计算系统(BiCoS),利用 CMOS 技术识别不同的模式。BiCoS 系统容易因横梁的寄生效应而产生各种可靠性问题。因此,我们开发了三维折叠电容横梁 Q3D 模型来研究横梁相关寄生件,并分析其对拟议系统的影响。横梁寄生的影响分为两种情况:首先,伊齐克维奇神经元的三种不同尖峰模式(常规尖峰、快速尖峰和颤振)在不同横梁尺寸下的变化情况。其次,分析其对模式识别率的影响,即模式识别率降低到 70%。应对这些挑战对于确保拟议系统的正确和稳健工作至关重要。因此,我们提出了有效克服和解决这些不利影响的解决方案。我们计算了识别每个图案所消耗的能量,平均所需的能量为 0.25 美元,与其他最先进的作品相比明显降低。电路采用 65nm 标准 CMOS 技术实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
8.50
自引率
2.20%
发文量
86
期刊介绍: The IEEE Journal on Emerging and Selected Topics in Circuits and Systems is published quarterly and solicits, with particular emphasis on emerging areas, special issues on topics that cover the entire scope of the IEEE Circuits and Systems (CAS) Society, namely the theory, analysis, design, tools, and implementation of circuits and systems, spanning their theoretical foundations, applications, and architectures for signal and information processing.
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