A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control

IF 4 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-30 DOI:10.1109/TCSII.2024.3470111

Jae-Yun Park;Jae-Won Nam

{"title":"A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control","authors":"Jae-Yun Park;Jae-Won Nam","doi":"10.1109/TCSII.2024.3470111","DOIUrl":null,"url":null,"abstract":"A qubit-control waveform generator utilizing a 4-channel time-interleaved \n<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>\n DAC is presented. A digital-to-analog converter (DAC) at 4.3 GS/s with an oversampling rate of 8 is fabricated in 65 nm CMOS technology. To enhance the linearity of the DAC, harmonic cancellation is proposed. Time-interleaving is applied in a \n<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>\n modulator to widen the bandwidth. A high operational speed is also achieved through an unrolling technique to the direct digital frequency synthesis (DDFS) digital core. To ensure robustness of the process-voltage-temperature (PVT) variations, temperature-insensitive bias is proposed, with implementation mainly based on digital circuits. The proposed \n<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>\n DAC consumes 256.04 mW of power, and the core area is \n<inline-formula> <tex-math>$0.11~mm^{2}$ </tex-math></inline-formula>\n. The signal-to-noise distortion ratio (SNDR) and the spurious free dynamic range (SFDR) after enabling harmonic cancellation are respectively 30.62 dB and 47.03 dB at 100 K temperature.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4663-4667"},"PeriodicalIF":4.0000,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10699418/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

A qubit-control waveform generator utilizing a 4-channel time-interleaved

$\Delta \Sigma $

DAC is presented. A digital-to-analog converter (DAC) at 4.3 GS/s with an oversampling rate of 8 is fabricated in 65 nm CMOS technology. To enhance the linearity of the DAC, harmonic cancellation is proposed. Time-interleaving is applied in a

$\Delta \Sigma $

modulator to widen the bandwidth. A high operational speed is also achieved through an unrolling technique to the direct digital frequency synthesis (DDFS) digital core. To ensure robustness of the process-voltage-temperature (PVT) variations, temperature-insensitive bias is proposed, with implementation mainly based on digital circuits. The proposed

$\Delta \Sigma $

DAC consumes 256.04 mW of power, and the core area is

$0.11~mm^{2}$

. The signal-to-noise distortion ratio (SNDR) and the spurious free dynamic range (SFDR) after enabling harmonic cancellation are respectively 30.62 dB and 47.03 dB at 100 K temperature.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

具有温度不敏感偏置和谐波消除功能的 4.3 GS/s 时交错 ΔΣ DAC，用于质子控制

本文介绍了一种利用 4 通道时间交错 $\Delta \Sigma $ DAC 的量子比特控制波形发生器。它采用 65 纳米 CMOS 技术制造出了一个 4.3 GS/s、过采样率为 8 的数模转换器 (DAC)。为提高 DAC 的线性度，提出了谐波消除方法。时间交错应用于 $\Delta \Sigma $ 调制器，以拓宽带宽。通过对直接数字频率合成（DDFS）数字内核采用解卷技术，还实现了较高的运行速度。为确保工艺-电压-温度（PVT）变化的鲁棒性，提出了温度敏感偏置，主要基于数字电路实现。所提出的 $\Delta \Sigma $ DAC 功耗为 256.04 mW，内核面积为 0.11~mm^{2}$ 。在 100 K 温度下，启用谐波消除后的信噪比（SNDR）和无杂散动态范围（SFDR）分别为 30.62 dB 和 47.03 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

IEEE Transactions on Circuits and Systems II: Express Briefs 工程技术-工程：电子与电气

CiteScore

7.90

自引率

20.50%

发文量

883

审稿时长

3.0 months

期刊介绍： TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: Circuits: Analog, Digital and Mixed Signal Circuits and Systems Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic Circuits and Systems, Power Electronics and Systems Software for Analog-and-Logic Circuits and Systems Control aspects of Circuits and Systems.

期刊最新文献

Table of Contents Guest Editorial Special Issue on the 2024 ISICAS: A CAS Journal Track Symposium IEEE Circuits and Systems Society Information IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control