Prototype Readout Electronics for Capacitive Detectors

Abstract

This article presents the description of a prototype readout electronics for capacitive detectors based on an application-specific integrated circuit (ASIC) designed specifically for the readout and pre-processing of signals from the flat resistive chambers of the SPD (spectrometer with pixel detectors) experiment at the NICA collider under construction at JINR (Joint Institute for Nuclear Research) in Dubna. The eight-channel ASIC is optimized to work with detectors featuring a characteristic impedance of the readout electrodes in the range of 35–110 Ω, with an equivalent input noise charge of no more than 2500 electrons. The ASIC includes adjustments for the threshold by the input charge in the range of 10–450 fC, hysteresis of the threshold characteristic in the range of 0–12%, and signal extension time in the range of 0.5–100 ns. The circuit was optimized to reduce jitter on the front edge (less than 10 ps) and power consumption (less than 25 mW per channel).