A Compact and Efficient Implementation of Modified MMF2 Encryption on FPGA

Abstract

The design of modern architectures with reduced capacity is an important challenge that electronics and computer engineers face. A modern architecture has been proposed for MMF2 encryption algorithm in this paper to reduce the occupied gate level. The algorithm uses an input block size of 64 b, an initiation key of 128 b with nine repetitions. The obtained results indicate to GE16023 decreasing in the hardware cost. The Verilog hardware language description language and QUARTUSII software have been used for simulation. The effectiveness of the method has been proven to be effective in the production of chips from CYCLONEII generation in 0.13- $\mu \text{m}$ CMOS technology.