{"title":"Optimized Fault Tolerant Core based ASIC Design for SRAM","authors":"T. Suresh, Z. Brijet","doi":"10.1504/IJMTM.2017.10011241","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":38792,"journal":{"name":"International Journal of Manufacturing Technology and Management","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Manufacturing Technology and Management","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1504/IJMTM.2017.10011241","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}
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