Huafang Ju, Xiang Li, J. Hsu, Shaohua Li, T. Su, Mo Liu, Kai Xiao
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引用次数: 2
Abstract
PCI-Express (PCIe) data rate continues to double generation by generation from PCIe 4.0 with 16Gbps, PCIe 5.0 with 32Gbps to PCIe 6.0 with 64Gbps in recent years. However, data center motherboard form factor and landing zone requirement remain the same, which implies all enablers in channel need to be improved to meet the maximum board routing length. Because PCB and connector are important components in the platform channel, besides their perspective performance, connector pin field PCB footprint design can also play a big role in channel solution space and PCB cost. In this paper, PCB routing optimization is addressed through the connector footprint optimization and the connector design innovation.
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