A hardware-efficient BCH encoder design

Abstract

Solid-state disks (SSD) are widely used storage devices in current consumer electronics. However, the enhancement of SSD data retention and reliability given the high read/write activity are critical research topics. Many error correction codes (ECC) have been developed in the literature to solve the aforementioned issues by embedding ECC design in flash memory. Bose-Chaudhuri-Hocquenghen (BCH) code is the most widely adopted ECC design owing to its error-correcting capability and hardware complexity. In this paper, we propose a hardware-efficient BCH coder that directly codes the input message without extra operations in the generation polynomial term. Compared with state-of-the-art designs, the proposed BCH coding design can save logic gate use and minimize the critical path delay with a 90-nm CMOS process.