Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983512
Hejia Cai, Yan Hu, Zhiliang Hong
A fully integrated CMOS power amplifier with 8-way current-voltage combining transformer is performed in tsmc65nm GP CMOS process. For the high power CMOS PA design, a novel hybrid-type power combining transformer is proposed. Four identical PAs are used and their output power are combined by an 8-way current-voltage combining transformer. With 3.3V power supply, the proposed power amplifier provides maximum output power of 35.2dBm and peak power added efficiency of 38.73% at 2.4GHz operating frequency. At 1dB compression point, the proposed power amplifier exhibits high output power of 33.1dBm with power add efficiency of 28.8%.
采用tsmc65nm GP CMOS工艺设计了一种带8路流压组合变压器的全集成CMOS功率放大器。针对大功率CMOS放大器的设计，提出了一种新型混合型功率组合变压器。使用四个相同的放大器，它们的输出功率由一个8路电流-电压组合变压器组合。在3.3V电源下，在2.4GHz工作频率下，功率放大器的最大输出功率为35.2dBm，峰值功率增加效率为38.73%。在1dB压缩点，该功率放大器的输出功率高达33.1dBm，功率增加效率为28.8%。
{"title":"A35.2 dBm CMOS RF Power Amplifier Using an 8-Way Current-Voltage Combining Transformer with Harmonic Control","authors":"Hejia Cai, Yan Hu, Zhiliang Hong","doi":"10.1109/ASICON47005.2019.8983512","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983512","url":null,"abstract":"A fully integrated CMOS power amplifier with 8-way current-voltage combining transformer is performed in tsmc65nm GP CMOS process. For the high power CMOS PA design, a novel hybrid-type power combining transformer is proposed. Four identical PAs are used and their output power are combined by an 8-way current-voltage combining transformer. With 3.3V power supply, the proposed power amplifier provides maximum output power of 35.2dBm and peak power added efficiency of 38.73% at 2.4GHz operating frequency. At 1dB compression point, the proposed power amplifier exhibits high output power of 33.1dBm with power add efficiency of 28.8%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124409728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983560
Weijie You, Chang Wu
In this paper, we propose a sparse convolutional neural network accelerator design on FPGAs. Similar to the DNNWEAVER architecture, our accelerator uses two-level hierarchy: multiple Processing Units (PUs) and each PU comprises a set of Processing Elements (PEs). To address the irregularity of sparse neural networks, we introduce a novel sparse dataflow for sparse CNN computing as well as weight merging method to balance the computation load on different PUs for better overall efficiency. We implement our design with 32 PUs and 14 PEs in each PU. When compared with DNNWEAVER on VGG16 network, our accelerator achieves 3.49x speedup and 3.05x energy saving on average when running at 150MHz on a Xilinx ZC706 board and reaches the speed of 400 GOPS.
{"title":"An Efficient Accelerator for Sparse Convolutional Neural Networks","authors":"Weijie You, Chang Wu","doi":"10.1109/ASICON47005.2019.8983560","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983560","url":null,"abstract":"In this paper, we propose a sparse convolutional neural network accelerator design on FPGAs. Similar to the DNNWEAVER architecture, our accelerator uses two-level hierarchy: multiple Processing Units (PUs) and each PU comprises a set of Processing Elements (PEs). To address the irregularity of sparse neural networks, we introduce a novel sparse dataflow for sparse CNN computing as well as weight merging method to balance the computation load on different PUs for better overall efficiency. We implement our design with 32 PUs and 14 PEs in each PU. When compared with DNNWEAVER on VGG16 network, our accelerator achieves 3.49x speedup and 3.05x energy saving on average when running at 150MHz on a Xilinx ZC706 board and reaches the speed of 400 GOPS.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127366353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/asicon47005.2019.8983633
T. Hiramoto, K. Satoh, T. Matsudai, W. Saito, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, H. Wakabayashi, K. Tsutsui, H. Iwai, A. Ogura, S. Nishizawa, I. Omura, H. Ohashi, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, Y. Numasawa
In this work, the switching of 3300V IGBTs by 5V gate drive voltage has been successfully demonstrated for the first time. IGBT was designed based on a scaling principle. Comparing with conventional 15V-driven non-scaled IGBTs, the tum-off tail current of the scaled devices significantly decreased. The improvement of $E_{mathrm{off}}$ vs $V_{mathrm{cesat}}$ relationship by 35% was achieved.
{"title":"Switching of 3300V Scaled IGBT by 5V Gate Drive","authors":"T. Hiramoto, K. Satoh, T. Matsudai, W. Saito, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, H. Wakabayashi, K. Tsutsui, H. Iwai, A. Ogura, S. Nishizawa, I. Omura, H. Ohashi, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, Y. Numasawa","doi":"10.1109/asicon47005.2019.8983633","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983633","url":null,"abstract":"In this work, the switching of 3300V IGBTs by 5V gate drive voltage has been successfully demonstrated for the first time. IGBT was designed based on a scaling principle. Comparing with conventional 15V-driven non-scaled IGBTs, the tum-off tail current of the scaled devices significantly decreased. The improvement of $E_{mathrm{off}}$ vs $V_{mathrm{cesat}}$ relationship by 35% was achieved.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125009888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/asicon47005.2019.8983591
MinhTri Tran, Yifei Sun, Y. Kobori, A. Kuwana, Haruo Kobayashi
This paper proposes a minimum output ripple and fixed operating frequency technique based on the modulation injection for a constant on-time (COT) ripple control converter. Basically, the modulation injection approach aims to add a modulation signal to the output inductor to fix the operating frequency on the discontinuous conduction mode (DCM) and does not affect the inductor current ripple injection. Moreover, the spread spectrum of pulse width modulation (PWM) method is also applied to reduce the electromagnetic interference (EMI) noise. The illustrative simulation results indicate that the proposed converter operates stably at a fixed switching frequency (1.6MHz), and the output ripple is kept very small (5mVpp). EMI noise levels are also kept below 50mV, which is compared to 5V desired voltage.
{"title":"Minimum Output Ripple and Fixed Operating Frequency Based on Modulation Injection for COT Ripple Control Converter","authors":"MinhTri Tran, Yifei Sun, Y. Kobori, A. Kuwana, Haruo Kobayashi","doi":"10.1109/asicon47005.2019.8983591","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983591","url":null,"abstract":"This paper proposes a minimum output ripple and fixed operating frequency technique based on the modulation injection for a constant on-time (COT) ripple control converter. Basically, the modulation injection approach aims to add a modulation signal to the output inductor to fix the operating frequency on the discontinuous conduction mode (DCM) and does not affect the inductor current ripple injection. Moreover, the spread spectrum of pulse width modulation (PWM) method is also applied to reduce the electromagnetic interference (EMI) noise. The illustrative simulation results indicate that the proposed converter operates stably at a fixed switching frequency (1.6MHz), and the output ripple is kept very small (5mVpp). EMI noise levels are also kept below 50mV, which is compared to 5V desired voltage.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"400 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123252164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983562
Chun-Ting Chen, Tsung-Yi Tsai, Y. Chiu, Chua-Chin Wang
In this investigation, an adaptive reset strategy of a 10-bit SAR-ADC particularly designed for the applications in FOG (fiber optic gyroscope) systems is demonstrated with TSMC 40 nm CMOS technology. The proposed adaptive reset approach takes advantage of high correlation of the phase shift generated by continuous FOG signals such that MSB bits of two consecutive samples likely remain the same, which implies there is no need to re-converted. By replacing conventional all-reset method with the adaptive-reset strategy, the throughput of the SAR ADC is theoretically increased up to around 100%. The sampling rate is increased by 2 times compared with the conventional counterpart.
{"title":"Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems","authors":"Chun-Ting Chen, Tsung-Yi Tsai, Y. Chiu, Chua-Chin Wang","doi":"10.1109/ASICON47005.2019.8983562","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983562","url":null,"abstract":"In this investigation, an adaptive reset strategy of a 10-bit SAR-ADC particularly designed for the applications in FOG (fiber optic gyroscope) systems is demonstrated with TSMC 40 nm CMOS technology. The proposed adaptive reset approach takes advantage of high correlation of the phase shift generated by continuous FOG signals such that MSB bits of two consecutive samples likely remain the same, which implies there is no need to re-converted. By replacing conventional all-reset method with the adaptive-reset strategy, the throughput of the SAR ADC is theoretically increased up to around 100%. The sampling rate is increased by 2 times compared with the conventional counterpart.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123786867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983496
Weiiie Xu, Yudi Zhao, Peng Huang, Xiaoyan Liu, Jinfeng Kang
This paper demonstrates the co-design of three-dimension (3D) Vertical Resistive Random Access Memory (RRAM) and the RRAM device. It presents a design consideration of 3D Vertical RRAM array in terms of array performance from the device point of view. A physics-based RRAM Spice model is used to evaluate the performance of 3D RRAM array, including write access voltage, read margin, energy consumption and switching speed. The effects of device parameters, device parasitic capacitance, device variation and the 3D array size are discussed for design consideration. The simulation results show that with carefully choosing the RRAM device material and structure, a fast-switching, low energy consumption 3D RRAM array can be realized.
{"title":"3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model","authors":"Weiiie Xu, Yudi Zhao, Peng Huang, Xiaoyan Liu, Jinfeng Kang","doi":"10.1109/ASICON47005.2019.8983496","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983496","url":null,"abstract":"This paper demonstrates the co-design of three-dimension (3D) Vertical Resistive Random Access Memory (RRAM) and the RRAM device. It presents a design consideration of 3D Vertical RRAM array in terms of array performance from the device point of view. A physics-based RRAM Spice model is used to evaluate the performance of 3D RRAM array, including write access voltage, read margin, energy consumption and switching speed. The effects of device parameters, device parasitic capacitance, device variation and the 3D array size are discussed for design consideration. The simulation results show that with carefully choosing the RRAM device material and structure, a fast-switching, low energy consumption 3D RRAM array can be realized.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126733379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983666
Leilei Jin, Wenjie Fu, Yu Zheng, Hao Yan
The impact of process variations on timing has become significant in advanced technology nodes. In this paper, a multivariate adaptive regression splines (MARS) delay model is proposed that considers both global and local process variations to characterize this impact more accurately. In order to obtain MAX operation results, the first three moments of MARS gate delay distribution are calculated, converting the timing distribution to a skew-normal representation. Eventually, based on an approximation MAX operation, the block-based SSTA propagates the arrival time through the timing diagram. Tested with 10 ISCAS85 benchmark circuits, the average mean squared error and standard deviation error of the path delay calculation are 0.52% and 0.88%.
{"title":"A Precise Block-Based Statistical Timing Analysis with MAX Approximation Using Multivariate Adaptive Regression Splines","authors":"Leilei Jin, Wenjie Fu, Yu Zheng, Hao Yan","doi":"10.1109/ASICON47005.2019.8983666","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983666","url":null,"abstract":"The impact of process variations on timing has become significant in advanced technology nodes. In this paper, a multivariate adaptive regression splines (MARS) delay model is proposed that considers both global and local process variations to characterize this impact more accurately. In order to obtain MAX operation results, the first three moments of MARS gate delay distribution are calculated, converting the timing distribution to a skew-normal representation. Eventually, based on an approximation MAX operation, the block-based SSTA propagates the arrival time through the timing diagram. Tested with 10 ISCAS85 benchmark circuits, the average mean squared error and standard deviation error of the path delay calculation are 0.52% and 0.88%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122878837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electroencephalogram (EEG) has significant applications on medical diagnosis and Brain Computer Interface (BCI). But the main obstacle of analyzing EEG signal is various types of noises to get actual information. Extracting important features is a key issue in this study. This paper uses the BCI Competition IV 2b motion imagery data, in which we provide a review of various prior art to determine the motion imaginary MI mission. Using machine learning to identify two different movements in the EEG signal, the data from nine subjects were analyzed by principal component analysis (PCA) combined with discrete wavelet (DWT) packet analysis. The extracted DWT feature is input into the support vector machine (SVM) classifier, and the experimental results shows that this method is better than traditional methods with a classification accuracy rate of 86.7%.
脑电图(EEG)在医学诊断和脑机接口(BCI)方面有着重要的应用。但是对脑电信号进行分析的主要障碍是各种各样的噪声，难以获得真实的信息。提取重要特征是本研究的关键问题。本文使用BCI Competition IV 2b运动图像数据，其中我们提供了各种现有技术的回顾，以确定运动想象的MI任务。采用机器学习识别脑电信号中的两种不同运动，并结合主成分分析(PCA)和离散小波包分析(DWT)对9名受试者的数据进行分析。将提取的DWT特征输入到支持向量机(SVM)分类器中，实验结果表明，该方法的分类准确率达到86.7%，优于传统方法。
{"title":"Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing","authors":"Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu","doi":"10.1109/ASICON47005.2019.8983523","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983523","url":null,"abstract":"Electroencephalogram (EEG) has significant applications on medical diagnosis and Brain Computer Interface (BCI). But the main obstacle of analyzing EEG signal is various types of noises to get actual information. Extracting important features is a key issue in this study. This paper uses the BCI Competition IV 2b motion imagery data, in which we provide a review of various prior art to determine the motion imaginary MI mission. Using machine learning to identify two different movements in the EEG signal, the data from nine subjects were analyzed by principal component analysis (PCA) combined with discrete wavelet (DWT) packet analysis. The extracted DWT feature is input into the support vector machine (SVM) classifier, and the experimental results shows that this method is better than traditional methods with a classification accuracy rate of 86.7%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129921938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983459
Hao Li, Hongmei Yu, Dongsheng Liu, Peng Liu, Bo Liu
Spin transfer torque magnetic random access memory (STT-MRAM) is an emerging non-volatile memory and is regarded as a next generation memory. Efforts have been made in its write scheme, but the proposed schemes suffer from high write power and reliability issues. In this paper, we propose a low-power high-reliability write scheme with real-time voltage sensing and control module. Write operations are immediately terminated when the states of cells switch as desire, and when the current state match the state to be switched into, write operations will be terminated directly. The scheme is implemented and simulated in SMIC 40nm Logic Low Leakage process. Simulation results show that write power is 0.106pJ/bit on average, which is 62.5% less than the traditional scheme, and the effective judgment range of write “0” and write “1” is 408mV and 275mV respectively which is 3.15 times larger than the best previously result to our knowledge to reach high write reliability.
{"title":"A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module","authors":"Hao Li, Hongmei Yu, Dongsheng Liu, Peng Liu, Bo Liu","doi":"10.1109/ASICON47005.2019.8983459","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983459","url":null,"abstract":"Spin transfer torque magnetic random access memory (STT-MRAM) is an emerging non-volatile memory and is regarded as a next generation memory. Efforts have been made in its write scheme, but the proposed schemes suffer from high write power and reliability issues. In this paper, we propose a low-power high-reliability write scheme with real-time voltage sensing and control module. Write operations are immediately terminated when the states of cells switch as desire, and when the current state match the state to be switched into, write operations will be terminated directly. The scheme is implemented and simulated in SMIC 40nm Logic Low Leakage process. Simulation results show that write power is 0.106pJ/bit on average, which is 62.5% less than the traditional scheme, and the effective judgment range of write “0” and write “1” is 408mV and 275mV respectively which is 3.15 times larger than the best previously result to our knowledge to reach high write reliability.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128599058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983589
W. Song, Yuxiang Fu, Qinyu Chen, Li Li, Chuan Zhang
Combined with cyclic redundancy check (CRC), SC list (SCL) decoder can achieve outstanding error correction performance, which is more obvious with increasing list size. However, the corresponding decoding complexity and latency increase with the list size. To this end, the selection of list size becomes essential for practical applications. A new artificial neural network (ANN) based framework is proposed in this paper to design a hardware-friendly adaptive SCL (DL-ASCL) decoder. First, the list size at each stage is predicted by an ANN predictor. The performance achieved based on the proposed DL-ASCL algorithm is close to the optimal SCL decoder with the same list size, especially in the high signal-to-noise ratio (SNR) region. Meanwhile, the computational complexity is significantly reduced compared with the conventional ones. Numerical results have demonstrated that the proposed deep learning based adaptive SCL decoder can achieve 56% computational complexity reduction compared with the conventional SCL decoder for the polar code with length 128 and rate 1/2. The hardware architecture of the adaptive SCL decoder based on the predicted list size is proposed and the folding technique is also adopted, which helps reduce the hardware cost by about 25%.
{"title":"ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes","authors":"W. Song, Yuxiang Fu, Qinyu Chen, Li Li, Chuan Zhang","doi":"10.1109/ASICON47005.2019.8983589","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983589","url":null,"abstract":"Combined with cyclic redundancy check (CRC), SC list (SCL) decoder can achieve outstanding error correction performance, which is more obvious with increasing list size. However, the corresponding decoding complexity and latency increase with the list size. To this end, the selection of list size becomes essential for practical applications. A new artificial neural network (ANN) based framework is proposed in this paper to design a hardware-friendly adaptive SCL (DL-ASCL) decoder. First, the list size at each stage is predicted by an ANN predictor. The performance achieved based on the proposed DL-ASCL algorithm is close to the optimal SCL decoder with the same list size, especially in the high signal-to-noise ratio (SNR) region. Meanwhile, the computational complexity is significantly reduced compared with the conventional ones. Numerical results have demonstrated that the proposed deep learning based adaptive SCL decoder can achieve 56% computational complexity reduction compared with the conventional SCL decoder for the polar code with length 128 and rate 1/2. The hardware architecture of the adaptive SCL decoder based on the predicted list size is proposed and the folding technique is also adopted, which helps reduce the hardware cost by about 25%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129272912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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