1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century最新文献
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633673
R. A. Snyder
This paper has been written following investigations within The Boeing Co. by individuals involved in ATE Systems design, development, definition and implementation over the issue of "standards". Results of those studies have been captured into this paper in the form of an analysis of the issues deriving from the central theme of ATE "commonality", impediments to "commonality", limitations imposed by the state of the art in ATE Systems development today and a proposed Lexicon for defining and describing the implied goal of "commonality" as that term is herein presented.
{"title":"A proposed structure and Lexicon for ATE commonality","authors":"R. A. Snyder","doi":"10.1109/AUTEST.1997.633673","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633673","url":null,"abstract":"This paper has been written following investigations within The Boeing Co. by individuals involved in ATE Systems design, development, definition and implementation over the issue of \"standards\". Results of those studies have been captured into this paper in the form of an analysis of the issues deriving from the central theme of ATE \"commonality\", impediments to \"commonality\", limitations imposed by the state of the art in ATE Systems development today and a proposed Lexicon for defining and describing the implied goal of \"commonality\" as that term is herein presented.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114521897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633613
J. Heiser
This paper gives an overview of the field of software testing. Some of the topics covered include: terminology; the role of software test; testing-related statistics; descriptions of functional, structural, static, and dynamic test techniques; and discussion of test management issues including the test implications of alternative software development models, test process improvement, and how much testing is enough. The paper ends with resources and references for further study.
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Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633554
E.G. Perkins, J.J. Wong
The VTest (Virtual Test) Program is producing an open environment and a methodology for Virtual Test development of TPSs for mixed-signal PCBs/LRMs. The VTest effort is paving the way for the integration of Design and Test by providing an EDA-based system solution emphasizing Design for Test and the Re-Use of Design information in Test Development. The VTest solution incorporates the CAE/CAD/CAT software tools necessary for virtual test of digital, analog and mixed-signal technology PCBs/LRMs, as well as the tools and methodologies that support the use of automatic test program generation for multiple target testers. This paper discusses the VTest solution architecture and the VTest approach to mixed-signal TPS development.
{"title":"VTest program mixed-signal virtual test approach","authors":"E.G. Perkins, J.J. Wong","doi":"10.1109/AUTEST.1997.633554","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633554","url":null,"abstract":"The VTest (Virtual Test) Program is producing an open environment and a methodology for Virtual Test development of TPSs for mixed-signal PCBs/LRMs. The VTest effort is paving the way for the integration of Design and Test by providing an EDA-based system solution emphasizing Design for Test and the Re-Use of Design information in Test Development. The VTest solution incorporates the CAE/CAD/CAT software tools necessary for virtual test of digital, analog and mixed-signal technology PCBs/LRMs, as well as the tools and methodologies that support the use of automatic test program generation for multiple target testers. This paper discusses the VTest solution architecture and the VTest approach to mixed-signal TPS development.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126471697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633641
V. Zagursky, D. Zibinch
Major principles for implementating the intercommunications of subscriber testing station operating under maximum throughput of transfer medium has been considered. The operating conditions and a conflict-free transfer medium access have been discussed. Circuitry and performance diagrams, also a circuit architecture for the main transfer medium component, the message signal switching sector have been given. Integration of such centres in implementing media of different topology has been discussed.
{"title":"High-throughput communication network for online subscriber testing station","authors":"V. Zagursky, D. Zibinch","doi":"10.1109/AUTEST.1997.633641","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633641","url":null,"abstract":"Major principles for implementating the intercommunications of subscriber testing station operating under maximum throughput of transfer medium has been considered. The operating conditions and a conflict-free transfer medium access have been discussed. Circuitry and performance diagrams, also a circuit architecture for the main transfer medium component, the message signal switching sector have been given. Integration of such centres in implementing media of different topology has been discussed.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126455632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633645
A. Ahlburn, J. Dean
This paper discusses the current efforts of the Air Force in moving our multitude of operational- and depot-level test systems towards a common architecture. Our current vision of what that architecture should be, and the programs we are participating in to achieve that common architecture, is covered.
{"title":"ATS modernization in the Air Force","authors":"A. Ahlburn, J. Dean","doi":"10.1109/AUTEST.1997.633645","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633645","url":null,"abstract":"This paper discusses the current efforts of the Air Force in moving our multitude of operational- and depot-level test systems towards a common architecture. Our current vision of what that architecture should be, and the programs we are participating in to achieve that common architecture, is covered.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127566517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633668
J. Scully
The TPS (Test Program Set) was initially conceptualized and structured to address external UUT (unit under test) testing. As the TPS evolved, it began to incorporate some interaction with UUT BIT (built in test). In view of current trends in prime system technology, it is now becoming increasingly clear that the TPS must be capable not only of accommodating UUTs that are BIT (and software) intensive, but also of integrating internal (BIT oriented) test features with external (test system oriented) test capability from the earliest stages of prime system (UUT) design. That is, the internal and external elements of the TPS, as well as the quantitative metrics through which test performance is measured, must be consolidated not only from the technical standpoint but also from the standpoint of acquisition philosophy.
{"title":"The consolidation of TPS elements within an integrated support concept","authors":"J. Scully","doi":"10.1109/AUTEST.1997.633668","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633668","url":null,"abstract":"The TPS (Test Program Set) was initially conceptualized and structured to address external UUT (unit under test) testing. As the TPS evolved, it began to incorporate some interaction with UUT BIT (built in test). In view of current trends in prime system technology, it is now becoming increasingly clear that the TPS must be capable not only of accommodating UUTs that are BIT (and software) intensive, but also of integrating internal (BIT oriented) test features with external (test system oriented) test capability from the earliest stages of prime system (UUT) design. That is, the internal and external elements of the TPS, as well as the quantitative metrics through which test performance is measured, must be consolidated not only from the technical standpoint but also from the standpoint of acquisition philosophy.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116424594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633664
M. Seavey
Historically Test Program Sets have been written "around" a particular ATE. Should anything change within the ATE that the TPS was written for, the TPS will be effected. This effect also applies towards TPS rehost/porting towards a different ATE. The following is a history of the problem(s) that continue, even today, to cost procuring agencies a great deal of money.
{"title":"TPS rehosting and station dependencies","authors":"M. Seavey","doi":"10.1109/AUTEST.1997.633664","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633664","url":null,"abstract":"Historically Test Program Sets have been written \"around\" a particular ATE. Should anything change within the ATE that the TPS was written for, the TPS will be effected. This effect also applies towards TPS rehost/porting towards a different ATE. The following is a history of the problem(s) that continue, even today, to cost procuring agencies a great deal of money.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116234087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633653
V. Zagursky
The paper deals with an improved technique for testing mixed signal system (MSS) as the system objects with the dynamic nonlinear and stochastic properties. A proposed technique makes it possible to estimate the dynamic characterization parameters typical as for spectral domain as for histogram testing. The implementation of the testing technique that is described is based on a broadband test signal that simulates actual operating conditions of MSS. By changing mode of the test-signal generation it may be possible to except masking of the signal knocked codes. The technique makes it possible to avoid the standard problems associated with precise estimation of the spectrum of a broadband signal. The proposed technique is well fitted for design for test (DFT) and built in self-test (BIST) schemes to integrated circuits including digital processing unit an on-chip ADC and DAC.
{"title":"Characterization techniques for mixed signal system","authors":"V. Zagursky","doi":"10.1109/AUTEST.1997.633653","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633653","url":null,"abstract":"The paper deals with an improved technique for testing mixed signal system (MSS) as the system objects with the dynamic nonlinear and stochastic properties. A proposed technique makes it possible to estimate the dynamic characterization parameters typical as for spectral domain as for histogram testing. The implementation of the testing technique that is described is based on a broadband test signal that simulates actual operating conditions of MSS. By changing mode of the test-signal generation it may be possible to except masking of the signal knocked codes. The technique makes it possible to avoid the standard problems associated with precise estimation of the spectrum of a broadband signal. The proposed technique is well fitted for design for test (DFT) and built in self-test (BIST) schemes to integrated circuits including digital processing unit an on-chip ADC and DAC.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116837986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633553
W.R. Dearborn, E.G. Perkins, J.J. Wong, D. Rolince
The need to reduce time to market and test development costs of Printed Circuit Card Assemblies (PCAs)/Line Replaceable Modules (LRMs) Test Program Sets (TPSs), has been a major concern for both industry and government. The lack of tools is the contributing factor to lengthy development times and high initial TPS development costs and subsequent higher costs of rehosting existing TPSs. These tools are Unit Under Test (UUT) and test resource simulation software, portable test information, and virtual test development for UUT design and test engineers. The Virtual Test (VTest) Program addresses the non-availability of appropriate tools and methodologies to support the design of TPSs during initial development and subsequent life-cycle maintenance periods. VTest will provide methodologies and tools that permit the design, capture, and simulation of tester independent test requirements, UUT models, and tester resource description information. The information developed will be utilized by multiple varieties of military and commercial testers, and will provide design requirements for test adapters.
{"title":"VTest system overview","authors":"W.R. Dearborn, E.G. Perkins, J.J. Wong, D. Rolince","doi":"10.1109/AUTEST.1997.633553","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633553","url":null,"abstract":"The need to reduce time to market and test development costs of Printed Circuit Card Assemblies (PCAs)/Line Replaceable Modules (LRMs) Test Program Sets (TPSs), has been a major concern for both industry and government. The lack of tools is the contributing factor to lengthy development times and high initial TPS development costs and subsequent higher costs of rehosting existing TPSs. These tools are Unit Under Test (UUT) and test resource simulation software, portable test information, and virtual test development for UUT design and test engineers. The Virtual Test (VTest) Program addresses the non-availability of appropriate tools and methodologies to support the design of TPSs during initial development and subsequent life-cycle maintenance periods. VTest will provide methodologies and tools that permit the design, capture, and simulation of tester independent test requirements, UUT models, and tester resource description information. The information developed will be utilized by multiple varieties of military and commercial testers, and will provide design requirements for test adapters.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129619322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633612
D. Pittman, J. Miller
Most software metrics and cost model tools are based upon the Line of Source Code unit measure of software. Lines of code have no equivalent in a diagrammatic-graphical programming paradigm. Programs developed in National Instrument's "G" or LabVIEW(R) development environment are represented as a hierarchy of Virtual Instruments. A virtual instrument (VI) consists of a virtual front panel window and a programmatic diagram window. The front panel provides the program interface and the diagram provides the implementation. This paper describes several features of the front panel and the diagram that influence program storage size, execution speed, memory requirements and maintainability. The VI Hierarchy is described along with the relationship of the hierarchy width and depth to code reuse and program complexity. The VI Profiler and LabVIEW(R) add-in products such as the "Professional G Developers Tool Kit" are examined, as is an adaptation of the McCabe Cyclomatic Complexity Metric.
{"title":"Software metrics for non-textual programming languages","authors":"D. Pittman, J. Miller","doi":"10.1109/AUTEST.1997.633612","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633612","url":null,"abstract":"Most software metrics and cost model tools are based upon the Line of Source Code unit measure of software. Lines of code have no equivalent in a diagrammatic-graphical programming paradigm. Programs developed in National Instrument's \"G\" or LabVIEW(R) development environment are represented as a hierarchy of Virtual Instruments. A virtual instrument (VI) consists of a virtual front panel window and a programmatic diagram window. The front panel provides the program interface and the diagram provides the implementation. This paper describes several features of the front panel and the diagram that influence program storage size, execution speed, memory requirements and maintainability. The VI Hierarchy is described along with the relationship of the hierarchy width and depth to code reuse and program complexity. The VI Profiler and LabVIEW(R) add-in products such as the \"Professional G Developers Tool Kit\" are examined, as is an adaptation of the McCabe Cyclomatic Complexity Metric.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129453481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century
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