Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531813
Noah Waller, Hunter Nauman, Derek Taylor, Rafael Del Carmen, J. Di
With the current business model and increasing complexity of hardware designs, third-party Intellectual Properties (IPs) are prevalently incorporated into first-party designs. The use of third-party IPs increases security concerns related to hardware Trojans inserted by attackers. Previous work on Golden Reference Matching focuses on matching with all entries within a single Golden Reference Library (GRL) containing whitelisted and blacklisted functionalities. This paper presents two new Golden Reference Libraries, Champion GRL and Functionality GRL, which were introduced along with coarse- grained and fine-grained asset reassignment to soft IPs and GRL entries in order to improve matching accuracy while simultaneously saving computational resources.
{"title":"Character Reassignment for Hardware Trojan Detection","authors":"Noah Waller, Hunter Nauman, Derek Taylor, Rafael Del Carmen, J. Di","doi":"10.1109/MWSCAS47672.2021.9531813","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531813","url":null,"abstract":"With the current business model and increasing complexity of hardware designs, third-party Intellectual Properties (IPs) are prevalently incorporated into first-party designs. The use of third-party IPs increases security concerns related to hardware Trojans inserted by attackers. Previous work on Golden Reference Matching focuses on matching with all entries within a single Golden Reference Library (GRL) containing whitelisted and blacklisted functionalities. This paper presents two new Golden Reference Libraries, Champion GRL and Functionality GRL, which were introduced along with coarse- grained and fine-grained asset reassignment to soft IPs and GRL entries in order to improve matching accuracy while simultaneously saving computational resources.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"35 1","pages":"861-864"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87427512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531862
Zisong Wang, Huan Wang, P. Heydari
The power amplifier (PA) for future 6G sub-THz wireless transmitters needs to offer wide bandwidth, high output power and reliable stability. This article, for the first time, studies the notion of wideband operation in sub-THz PAs incorporating neutralization techniques. Quantitative analyses are conducted to better understand the trade-offs among Gmax, stability Kf, and the bandwidth for a widely adopted differential pair under (over) neutralization. Next, a comparative study for transmission-line (T-line)-based and transformer-based matching networks is undertaken to give insights to the design of inter-stage matching networks. It is shown that transformer-based matching networks essentially introduce multi-stagger tuning, thereby leading to higher operation bandwidth suitable for 6G applications.
{"title":"CMOS Power-Amplifier Design Perspectives for 6G Wireless Communications","authors":"Zisong Wang, Huan Wang, P. Heydari","doi":"10.1109/MWSCAS47672.2021.9531862","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531862","url":null,"abstract":"The power amplifier (PA) for future 6G sub-THz wireless transmitters needs to offer wide bandwidth, high output power and reliable stability. This article, for the first time, studies the notion of wideband operation in sub-THz PAs incorporating neutralization techniques. Quantitative analyses are conducted to better understand the trade-offs among Gmax, stability Kf, and the bandwidth for a widely adopted differential pair under (over) neutralization. Next, a comparative study for transmission-line (T-line)-based and transformer-based matching networks is undertaken to give insights to the design of inter-stage matching networks. It is shown that transformer-based matching networks essentially introduce multi-stagger tuning, thereby leading to higher operation bandwidth suitable for 6G applications.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"93 1","pages":"753-756"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80021431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531776
S. Gardner, M. Haider, L. Moradi, V. Vantsevich
Image classification is typically performed with highly trained feed-forward machine learning algorithms like deep neural networks and support vector machines. The image can be treated as a time-series input when applied to the network multiple times, opening the way for recurrent neural networks to perform tasks like image classification, semantic segmentation and auto-encoding. With this approach, ultra-fast training, network optimization, and short-term memory effects allows for dynamic, low-volume datasets to be quickly learned without heavy image pre-processing or feature extraction; the main limitation being that input images need labeled output images for training, as is also true of most standard approaches. In this work, the MNIST handwritten digit dataset is used as a benchmark to evaluate metrics of a modified Echo State Network for static image classification. The image array is passed through a noise filter multiple times as the Echo State Network converges to a classification. This highly dynamic approach easily adapts to sequential image (video) tasks like object tracking and is effective with small datasets. Classification rates reach 95.3% with sample size of 10000 handwritten digits and training time of approximately 5 minutes. Progression of this research enables discrete image and time-series classification under a single algorithm, with low computing power and memory requirements.
{"title":"A Modified Echo State Network for Time Independent Image Classification","authors":"S. Gardner, M. Haider, L. Moradi, V. Vantsevich","doi":"10.1109/MWSCAS47672.2021.9531776","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531776","url":null,"abstract":"Image classification is typically performed with highly trained feed-forward machine learning algorithms like deep neural networks and support vector machines. The image can be treated as a time-series input when applied to the network multiple times, opening the way for recurrent neural networks to perform tasks like image classification, semantic segmentation and auto-encoding. With this approach, ultra-fast training, network optimization, and short-term memory effects allows for dynamic, low-volume datasets to be quickly learned without heavy image pre-processing or feature extraction; the main limitation being that input images need labeled output images for training, as is also true of most standard approaches. In this work, the MNIST handwritten digit dataset is used as a benchmark to evaluate metrics of a modified Echo State Network for static image classification. The image array is passed through a noise filter multiple times as the Echo State Network converges to a classification. This highly dynamic approach easily adapts to sequential image (video) tasks like object tracking and is effective with small datasets. Classification rates reach 95.3% with sample size of 10000 handwritten digits and training time of approximately 5 minutes. Progression of this research enables discrete image and time-series classification under a single algorithm, with low computing power and memory requirements.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"15 1","pages":"255-258"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80745132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531911
N. Gupta, H. Shrimali, A. Makosiej, A. Vladimirescu, A. Amara
This paper presents a novel TFET-CMOS co-integrated comparator-less, energy-efficient ADC architecture. The design utilizes the Negative Differential Resistance property of TFETs to generate thermometer code without using comparators. The design supports Dynamic Voltage Frequency Scaling. Binary-weighted TFET device sizing is used to generate thermometer code. TFETs used in this work are compatible with a 28nm FDSOI-CMOS process for fabrication. The most relevant performance numbers for 3- to 10-bit ADC architectures include speed of operation of 68 MHz with an ENOB evaluated greater than 2.38 for the 3-bit ADC; the FOM is in the range of 0.07 to 1.3 fJ/conversion for 3- to 10-bit designs with supply voltages from 0.4V to 1.2V, respectively. The proposed 5- and 6-bit designs show 46x [1] and 265x [2] improvement in FOM, respectively.
{"title":"Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC","authors":"N. Gupta, H. Shrimali, A. Makosiej, A. Vladimirescu, A. Amara","doi":"10.1109/MWSCAS47672.2021.9531911","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531911","url":null,"abstract":"This paper presents a novel TFET-CMOS co-integrated comparator-less, energy-efficient ADC architecture. The design utilizes the Negative Differential Resistance property of TFETs to generate thermometer code without using comparators. The design supports Dynamic Voltage Frequency Scaling. Binary-weighted TFET device sizing is used to generate thermometer code. TFETs used in this work are compatible with a 28nm FDSOI-CMOS process for fabrication. The most relevant performance numbers for 3- to 10-bit ADC architectures include speed of operation of 68 MHz with an ENOB evaluated greater than 2.38 for the 3-bit ADC; the FOM is in the range of 0.07 to 1.3 fJ/conversion for 3- to 10-bit designs with supply voltages from 0.4V to 1.2V, respectively. The proposed 5- and 6-bit designs show 46x [1] and 265x [2] improvement in FOM, respectively.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"57 1","pages":"297-300"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84960553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531708
Hendrik Wöhrle, M. D. L. Alvarez, Fabian Schlenke, A. Walsemann, M. Karagounis, F. Kirchner
In this paper, we present an ASIC based on 22FDX/FDSOI technology for the detection of atrial fibrillation in human electrocardiograms using neural networks. The ASIC consists of a RISC-V core for supporting software components and an application-specific machine learning IP core (ML-IP), which is used to implement the computationally intensive inference. The ASIC was designed for maximum energy efficiency. A special feature of the ML-IP is its modular, generic and scalable design of the ML-IP which allows to specify the quantization of each computational operation, the degree of parallelization and the architecture of the neural network. This in turn allows the use of ML-based optimization techniques to perform co-optimization for hardware design and architecture of the neural network (NNs). Here, a multi-objective optimization of the overall system is performed with respect to computational efficiency at a given classification accuracy and speed by using a multi-objective optimization, which is carried out using a probabilistic surrogate model. This model tries to find the optimal neural network architecture with a minimum number of training, simulation and evaluation steps.
{"title":"Surrogate Model based Co-Optimization of Deep Neural Network Hardware Accelerators","authors":"Hendrik Wöhrle, M. D. L. Alvarez, Fabian Schlenke, A. Walsemann, M. Karagounis, F. Kirchner","doi":"10.1109/MWSCAS47672.2021.9531708","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531708","url":null,"abstract":"In this paper, we present an ASIC based on 22FDX/FDSOI technology for the detection of atrial fibrillation in human electrocardiograms using neural networks. The ASIC consists of a RISC-V core for supporting software components and an application-specific machine learning IP core (ML-IP), which is used to implement the computationally intensive inference. The ASIC was designed for maximum energy efficiency. A special feature of the ML-IP is its modular, generic and scalable design of the ML-IP which allows to specify the quantization of each computational operation, the degree of parallelization and the architecture of the neural network. This in turn allows the use of ML-based optimization techniques to perform co-optimization for hardware design and architecture of the neural network (NNs). Here, a multi-objective optimization of the overall system is performed with respect to computational efficiency at a given classification accuracy and speed by using a multi-objective optimization, which is carried out using a probabilistic surrogate model. This model tries to find the optimal neural network architecture with a minimum number of training, simulation and evaluation steps.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"28 1","pages":"40-45"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78525140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531918
M. Saberi, S. Gardner, M. Haider
With the ever increasing world population, there is a critical need for healthy food resources. Fish are the most environmentally-friendly animal protein to produce, efficiently converting feed into meat while generating a fraction of the greenhouse gasses of livestock production. Therefore, fish farming is one of the most important fields for a sustainable future. Since there is no way for fishes in fish farming pools to migrate into healthier water, a key factor in this industry is to maintain the water quality in standard conditions. Out of different key measurements used to quantify water quality, pH is among the essentials. In this study a portable, cheap, non contact, reusable, and machine learning-based pH sensing system is introduced. This helps farmers to quantify the pH quality of their pools without spending significant amounts of money on measurement equipment. This work introduces a sensitive, non-invasive and reflection-based optical sensor along with an Autoencoder-ESN framework for pH sensing. Using the Autoencoder guarantees at least 5 percent better classification in comparison with simple Echo State Networks. Long lifetimes of the sensor along with high sensitivity of the machine learning algorithm makes this system valuable for local farmers.
{"title":"A Machine Learning Based Smart Contact-less pH Sensing and Classification","authors":"M. Saberi, S. Gardner, M. Haider","doi":"10.1109/MWSCAS47672.2021.9531918","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531918","url":null,"abstract":"With the ever increasing world population, there is a critical need for healthy food resources. Fish are the most environmentally-friendly animal protein to produce, efficiently converting feed into meat while generating a fraction of the greenhouse gasses of livestock production. Therefore, fish farming is one of the most important fields for a sustainable future. Since there is no way for fishes in fish farming pools to migrate into healthier water, a key factor in this industry is to maintain the water quality in standard conditions. Out of different key measurements used to quantify water quality, pH is among the essentials. In this study a portable, cheap, non contact, reusable, and machine learning-based pH sensing system is introduced. This helps farmers to quantify the pH quality of their pools without spending significant amounts of money on measurement equipment. This work introduces a sensitive, non-invasive and reflection-based optical sensor along with an Autoencoder-ESN framework for pH sensing. Using the Autoencoder guarantees at least 5 percent better classification in comparison with simple Echo State Networks. Long lifetimes of the sensor along with high sensitivity of the machine learning algorithm makes this system valuable for local farmers.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"12 1","pages":"1049-1052"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78804837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531773
Shadi Sheikhfaal, Meghana Reddy Vangala, Adekunle A. Adepegba, R. Demara
In this paper, we develop a low-power and area-efficient hardware implementation for Long Short-Term Memory (LSTM) networks as a type of Recurrent Neural Network (RNN). The LSTM network herein employs Resistive Random-Access Memory (ReRAM) based synapses along with spin-based non-binary neurons to achieve energy-efficiency while maintaining comparable accuracy. The proposed neuron provides a novel activation mechanism with five levels of output accuracy to mimic the ideal tanh and sigmoid activation functions. We have examined the performance of an LSTM network for name prediction purposes utilizing ideal, binary, and the proposed non-binary neuron. The comparison of the results shows that our proposed neuron can achieve up to 85% accuracy and perplexity of 1.56, which attains performance similar to algorithmic expectations of near-ideal neurons. The simulations show that our proposed neuron achieves up to 34-fold improvement in energy efficiency and 2-fold area reduction compared to the CMOS-based non-binary designs.
{"title":"Long Short-Term Memory with Spin-Based Binary and Non-Binary Neurons","authors":"Shadi Sheikhfaal, Meghana Reddy Vangala, Adekunle A. Adepegba, R. Demara","doi":"10.1109/MWSCAS47672.2021.9531773","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531773","url":null,"abstract":"In this paper, we develop a low-power and area-efficient hardware implementation for Long Short-Term Memory (LSTM) networks as a type of Recurrent Neural Network (RNN). The LSTM network herein employs Resistive Random-Access Memory (ReRAM) based synapses along with spin-based non-binary neurons to achieve energy-efficiency while maintaining comparable accuracy. The proposed neuron provides a novel activation mechanism with five levels of output accuracy to mimic the ideal tanh and sigmoid activation functions. We have examined the performance of an LSTM network for name prediction purposes utilizing ideal, binary, and the proposed non-binary neuron. The comparison of the results shows that our proposed neuron can achieve up to 85% accuracy and perplexity of 1.56, which attains performance similar to algorithmic expectations of near-ideal neurons. The simulations show that our proposed neuron achieves up to 34-fold improvement in energy efficiency and 2-fold area reduction compared to the CMOS-based non-binary designs.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"35 1","pages":"317-320"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76710510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531745
Farid Kenarangi, Inna Partin-Vaisband
Mixed-signal integrated circuits (ICs) for machine learning (ML) have been demonstrated as a powerful tool for efficient and accurate classification of large volumes of complex data. Despite the growing interest in ML ICs, the design process of mixed-signal ML classifiers is dominated by ad hoc approaches. In this paper, a rapid synthesizer is developed in Python (PySyn) for designing compact power-efficient high-performance ML classifiers. Circuit-level ML library is designed and leveraged within the flow. System-level tradeoffs are generated with PySyn and utilized to iteratively adjust the ML performance. PySyn is demonstrated with a state-of-the-art classifier, generating optimized netlists under input constraints.
{"title":"PySyn: A Rapid Synthesis for Mixed-Signal Machine Learning Classification","authors":"Farid Kenarangi, Inna Partin-Vaisband","doi":"10.1109/MWSCAS47672.2021.9531745","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531745","url":null,"abstract":"Mixed-signal integrated circuits (ICs) for machine learning (ML) have been demonstrated as a powerful tool for efficient and accurate classification of large volumes of complex data. Despite the growing interest in ML ICs, the design process of mixed-signal ML classifiers is dominated by ad hoc approaches. In this paper, a rapid synthesizer is developed in Python (PySyn) for designing compact power-efficient high-performance ML classifiers. Circuit-level ML library is designed and leveraged within the flow. System-level tradeoffs are generated with PySyn and utilized to iteratively adjust the ML performance. PySyn is demonstrated with a state-of-the-art classifier, generating optimized netlists under input constraints.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"15 1","pages":"712-717"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77037859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531718
Genevieve Sapijaszko, W. Mikhael
Facial recognition systems have seen widespread use in numerous applications, including identity verification for phone security, missing person identification, and forensic investigations. The purpose of this study is to improve both the speed and accuracy of a facial recognition system, thus enhancing its suitability for real-world applications. The proposed system reduces overall computational complexity by using simple algorithms and transforms such as grayscaling, a two-dimensional discrete wavelet transform, and a two-dimensional discrete cosine transform. The classification algorithm increases accuracy by using a straight-forward multilayer sigmoid neural network, which better correlates the input and output data than existing methods. The recognition system is tested with four freely accessible datasets: the ORL, YALE, FERET-c, and FEI. A test set based on the combination of all datasets is also utilized to evaluate the system performance. Results show that the system still maintains high recognition rates despite reducing complexity compared to popular existing methods.
{"title":"Facial Recognition System Using DWT, DCT, and Multilayer Sigmoid Neural Network Classifier","authors":"Genevieve Sapijaszko, W. Mikhael","doi":"10.1109/MWSCAS47672.2021.9531718","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531718","url":null,"abstract":"Facial recognition systems have seen widespread use in numerous applications, including identity verification for phone security, missing person identification, and forensic investigations. The purpose of this study is to improve both the speed and accuracy of a facial recognition system, thus enhancing its suitability for real-world applications. The proposed system reduces overall computational complexity by using simple algorithms and transforms such as grayscaling, a two-dimensional discrete wavelet transform, and a two-dimensional discrete cosine transform. The classification algorithm increases accuracy by using a straight-forward multilayer sigmoid neural network, which better correlates the input and output data than existing methods. The recognition system is tested with four freely accessible datasets: the ORL, YALE, FERET-c, and FEI. A test set based on the combination of all datasets is also utilized to evaluate the system performance. Results show that the system still maintains high recognition rates despite reducing complexity compared to popular existing methods.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"19 1","pages":"533-536"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73153920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531744
Seyedfakhreddin Nabavi, A. Pourzadi, S. Bhadra
Over past decades, light-emitting diodes (LEDs) have been identified as an ordinary part of many industrial and biomedical applications and many attempts done to enlarge their versatility. This paper proposes a 5-bit current steering DAC with the capability of driving two LEDs in a commercial OSRAM photoplethysmography (PPG) sensor which have different forward voltages. The DAC operates based on the thermometer-code conversion and is designed for 65 nm TSMC technology. Combined with a LED driver circuit it is able to convert a 5-bit digital input to an LED current signal. Results indicate that the implemented DAC can reach up to 50 M samples per second (MS/s) and changing its input by 1 LSB leads to 940 µA variation in the LED current. It is shown that the DAC system can independently drive two LEDs with the forward voltages of 1.8 V and 2.8 V at different time instants. According to the binary input signal of the DAC, the amplitude of the driving current signal, which identifies the brightness of LEDs, can be varied between 3.29 mA and 32.45 mA at a maximum frequency of 50 KS/s.
{"title":"Design of a 5-Bit Current Steering DAC for Driving High Forward Voltage LEDs","authors":"Seyedfakhreddin Nabavi, A. Pourzadi, S. Bhadra","doi":"10.1109/MWSCAS47672.2021.9531744","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531744","url":null,"abstract":"Over past decades, light-emitting diodes (LEDs) have been identified as an ordinary part of many industrial and biomedical applications and many attempts done to enlarge their versatility. This paper proposes a 5-bit current steering DAC with the capability of driving two LEDs in a commercial OSRAM photoplethysmography (PPG) sensor which have different forward voltages. The DAC operates based on the thermometer-code conversion and is designed for 65 nm TSMC technology. Combined with a LED driver circuit it is able to convert a 5-bit digital input to an LED current signal. Results indicate that the implemented DAC can reach up to 50 M samples per second (MS/s) and changing its input by 1 LSB leads to 940 µA variation in the LED current. It is shown that the DAC system can independently drive two LEDs with the forward voltages of 1.8 V and 2.8 V at different time instants. According to the binary input signal of the DAC, the amplitude of the driving current signal, which identifies the brightness of LEDs, can be varied between 3.29 mA and 32.45 mA at a maximum frequency of 50 KS/s.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"25 1","pages":"1045-1048"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74259344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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