基于RNS的Wallace树乘法器的高效结构

2008 51st Midwest Symposium on Circuits and Systems Pub Date : 2008-09-03 DOI:10.1109/MWSCAS.2008.4616776

P. P. Kundu, Oishila Bandyopadhyay, Amitabha Sinha

{"title":"基于RNS的Wallace树乘法器的高效结构","authors":"P. P. Kundu, Oishila Bandyopadhyay, Amitabha Sinha","doi":"10.1109/MWSCAS.2008.4616776","DOIUrl":null,"url":null,"abstract":"In this paper a novel technique to determine the optimal moduli set has been introduced and an efficient RNS multiplier based on Wallace tree multiplier (for 32 bit arithmetic unit) for DSP applications is presented. Performance analysis on a number of DSP functions like FIR, FFT etc. clearly indicates the novelty of the scheme.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"55 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"An efficient architecture of RNS based Wallace Tree multiplier for DSP applications\",\"authors\":\"P. P. Kundu, Oishila Bandyopadhyay, Amitabha Sinha\",\"doi\":\"10.1109/MWSCAS.2008.4616776\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a novel technique to determine the optimal moduli set has been introduced and an efficient RNS multiplier based on Wallace tree multiplier (for 32 bit arithmetic unit) for DSP applications is presented. Performance analysis on a number of DSP functions like FIR, FFT etc. clearly indicates the novelty of the scheme.\",\"PeriodicalId\":118637,\"journal\":{\"name\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"volume\":\"55 3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-09-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2008.4616776\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 51st Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2008.4616776","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

本文介绍了一种确定最优模集的新方法，并提出了一种基于Wallace树乘法器(适用于32位算术单元)的高效RNS乘法器。对FIR、FFT等多个DSP功能的性能分析表明了该方案的新颖性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

An efficient architecture of RNS based Wallace Tree multiplier for DSP applications

In this paper a novel technique to determine the optimal moduli set has been introduced and an efficient RNS multiplier based on Wallace tree multiplier (for 32 bit arithmetic unit) for DSP applications is presented. Performance analysis on a number of DSP functions like FIR, FFT etc. clearly indicates the novelty of the scheme.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2008 51st Midwest Symposium on Circuits and Systems

自引率

0.00%

发文量