Design of a one-megacycle iteration rate DDA

This paper describes the design of a parallel digital differential analyzer which operates at a rate of one million iterations per second. SPEDAC (Solid-State Parallel Expandable Differential Analyzer Computer) features parallel organization of the integrators, serial-parallel arithmetic within the integration cycle, 26-bit word length, and the integral inclusion of a digital function generator. The computer is programmed in analog computer fashion by means of plugboard interconnection of the integrators. To achieve the one megacycle iteration rate, the arithmetic circuits operate at a six megacycle clock rate performing trapezoidal integration. The use of a parallel magnetic core memory permits direct parallel communication and hybrid operation with external large scale general purpose digital computers.