{"title":"通过元胞自动机在顺序电路中嵌入测试模式","authors":"F. Fummi, D. Sciuto, M. Serra","doi":"10.1109/ASPDAC.1995.486390","DOIUrl":null,"url":null,"abstract":"The embedding of test patterns into a sequential circuit is the main topic of this paper. Deterministic test patterns for the sequential circuit under test are chosen to be embedded into hybrid cellular automata (CA). Test identification and CA synthesis are performed in parallel thus overcoming results achieved by embedding pre-computed vectors. The theory of sequential test generation under such a constraint is provided and the feasibility of the proposed testing methodology is shown on benchmarks.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Test pattern embedding in sequential circuits through cellular automata\",\"authors\":\"F. Fummi, D. Sciuto, M. Serra\",\"doi\":\"10.1109/ASPDAC.1995.486390\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The embedding of test patterns into a sequential circuit is the main topic of this paper. Deterministic test patterns for the sequential circuit under test are chosen to be embedded into hybrid cellular automata (CA). Test identification and CA synthesis are performed in parallel thus overcoming results achieved by embedding pre-computed vectors. The theory of sequential test generation under such a constraint is provided and the feasibility of the proposed testing methodology is shown on benchmarks.\",\"PeriodicalId\":119232,\"journal\":{\"name\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1995.486390\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1995.486390","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Test pattern embedding in sequential circuits through cellular automata
The embedding of test patterns into a sequential circuit is the main topic of this paper. Deterministic test patterns for the sequential circuit under test are chosen to be embedded into hybrid cellular automata (CA). Test identification and CA synthesis are performed in parallel thus overcoming results achieved by embedding pre-computed vectors. The theory of sequential test generation under such a constraint is provided and the feasibility of the proposed testing methodology is shown on benchmarks.
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