Jing-Shiun Lin, Ming-Der Shieh, Chungguang Liu, Der-Wei Yang
{"title":"高效的高并行涡轮解码器3GPP LTE-Advanced","authors":"Jing-Shiun Lin, Ming-Der Shieh, Chungguang Liu, Der-Wei Yang","doi":"10.1109/VLSI-DAT.2015.7114513","DOIUrl":null,"url":null,"abstract":"Turbo codes have been widely adopted in latest wireless communication systems due to their excellent error correction capability. In 3GPP LTE-Advanced systems, a peak data rate of up to 1 Gbps should be satisfied. To meet this throughput requirement, several turbo decoding algorithms aimed at achieving highly parallel architecture have been investigated. However, the resulting hardware cost of turbo decoders is increased considerably with increasing parallelism. This paper presents a modified parallel-window decoding algorithm to reduce the warm-up computation ratio per each decoding window. In addition, a dual-mode computing schedule is proposed to support the requirement of various code rates and block lengths. Experimental results reveal that the proposed design, implemented in the TSMC 90-nm CMOS process, can achieve the highest throughput rate of 1.45 Gbps and improve the normalized area efficiency by about 24.53% compared to the existing 3GPP-LTE-Advanced turbo decoders.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"8 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Efficient highly-parallel turbo decoder for 3GPP LTE-Advanced\",\"authors\":\"Jing-Shiun Lin, Ming-Der Shieh, Chungguang Liu, Der-Wei Yang\",\"doi\":\"10.1109/VLSI-DAT.2015.7114513\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Turbo codes have been widely adopted in latest wireless communication systems due to their excellent error correction capability. In 3GPP LTE-Advanced systems, a peak data rate of up to 1 Gbps should be satisfied. To meet this throughput requirement, several turbo decoding algorithms aimed at achieving highly parallel architecture have been investigated. However, the resulting hardware cost of turbo decoders is increased considerably with increasing parallelism. This paper presents a modified parallel-window decoding algorithm to reduce the warm-up computation ratio per each decoding window. In addition, a dual-mode computing schedule is proposed to support the requirement of various code rates and block lengths. Experimental results reveal that the proposed design, implemented in the TSMC 90-nm CMOS process, can achieve the highest throughput rate of 1.45 Gbps and improve the normalized area efficiency by about 24.53% compared to the existing 3GPP-LTE-Advanced turbo decoders.\",\"PeriodicalId\":369130,\"journal\":{\"name\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"volume\":\"8 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT.2015.7114513\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114513","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficient highly-parallel turbo decoder for 3GPP LTE-Advanced
Turbo codes have been widely adopted in latest wireless communication systems due to their excellent error correction capability. In 3GPP LTE-Advanced systems, a peak data rate of up to 1 Gbps should be satisfied. To meet this throughput requirement, several turbo decoding algorithms aimed at achieving highly parallel architecture have been investigated. However, the resulting hardware cost of turbo decoders is increased considerably with increasing parallelism. This paper presents a modified parallel-window decoding algorithm to reduce the warm-up computation ratio per each decoding window. In addition, a dual-mode computing schedule is proposed to support the requirement of various code rates and block lengths. Experimental results reveal that the proposed design, implemented in the TSMC 90-nm CMOS process, can achieve the highest throughput rate of 1.45 Gbps and improve the normalized area efficiency by about 24.53% compared to the existing 3GPP-LTE-Advanced turbo decoders.
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