通信系统中Gbps pcb的SI和设计考虑

IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI:10.1109/EPEP.2001.967665

Z. Mu, K. Willis

{"title":"通信系统中Gbps pcb的SI和设计考虑","authors":"Z. Mu, K. Willis","doi":"10.1109/EPEP.2001.967665","DOIUrl":null,"url":null,"abstract":"This paper covers the board level signal integrity issues at Gbps rates, impact of pre-emphasis, interconnect design considerations, and plane configuration techniques for power delivery. Pre-defined rules can be drawn from the discussion to guide high speed board designs.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"SI and design considerations for Gbps PCBs in communication systems\",\"authors\":\"Z. Mu, K. Willis\",\"doi\":\"10.1109/EPEP.2001.967665\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper covers the board level signal integrity issues at Gbps rates, impact of pre-emphasis, interconnect design considerations, and plane configuration techniques for power delivery. Pre-defined rules can be drawn from the discussion to guide high speed board designs.\",\"PeriodicalId\":174339,\"journal\":{\"name\":\"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)\",\"volume\":\"55 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2001.967665\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2001.967665","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

本文涵盖了Gbps速率下的板级信号完整性问题，预强调的影响，互连设计考虑因素以及功率传输的平面配置技术。从讨论中可以得出预先定义的规则来指导高速板的设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

SI and design considerations for Gbps PCBs in communication systems

This paper covers the board level signal integrity issues at Gbps rates, impact of pre-emphasis, interconnect design considerations, and plane configuration techniques for power delivery. Pre-defined rules can be drawn from the discussion to guide high speed board designs.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)

自引率

0.00%

发文量