{"title":"计数器寄存器的设计","authors":"Ferdynand Wagner","doi":"10.1049/IJ-CDT.1979.0015","DOIUrl":null,"url":null,"abstract":"The paper describes a method of designing counter registers. Two important features of the method are that it produces a minimal design and that it is guaranteed to avoid jamming. The method may be applied to the synthesis of any counter registers used, for example, as binary-sequence generators, word generators, counters, pseudorandom binary-sequence generators etc. The paper contains examples which demonstrate the design procedure, and gives some results relating to minimal counter registers.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of counter registers\",\"authors\":\"Ferdynand Wagner\",\"doi\":\"10.1049/IJ-CDT.1979.0015\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper describes a method of designing counter registers. Two important features of the method are that it produces a minimal design and that it is guaranteed to avoid jamming. The method may be applied to the synthesis of any counter registers used, for example, as binary-sequence generators, word generators, counters, pseudorandom binary-sequence generators etc. The paper contains examples which demonstrate the design procedure, and gives some results relating to minimal counter registers.\",\"PeriodicalId\":344610,\"journal\":{\"name\":\"Iee Journal on Computers and Digital Techniques\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1979-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Iee Journal on Computers and Digital Techniques\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1049/IJ-CDT.1979.0015\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iee Journal on Computers and Digital Techniques","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/IJ-CDT.1979.0015","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The paper describes a method of designing counter registers. Two important features of the method are that it produces a minimal design and that it is guaranteed to avoid jamming. The method may be applied to the synthesis of any counter registers used, for example, as binary-sequence generators, word generators, counters, pseudorandom binary-sequence generators etc. The paper contains examples which demonstrate the design procedure, and gives some results relating to minimal counter registers.