Inter-chip wireless interconnect system over PCB medium channels

A design scheme is proposed for wireless interconnection communication between chips. The PCB medium channel is built with absorber layers. Two chip pin antennas are designed and simulated. Their scattering parameters are extracted and compared with three different cases. It evaluates the bit error rate (BER) performance via a interconnect communication model with a coherent binary phase shift keying (BPSK) modulator and demodulator. Simulation results show that the designed system performance degrades with the increase of separation distance and signal noise ratio. A high data rate at 1 Gb/s with a low BER <; 10-5 can be achieved with the transmitted power of 10 dBm.