Design of Low-Power Highly Accurate CMOS Potentiostat Using the gm/ID Methodology

This paper presents the design of CMOS potentiostats using the gm/ID methodology. We investigate the gm/ID methodology as a systematic framework for optimal potentiostat design in terms of power dissipation, noise and area, the three most important potentiostat performance criteria. To this end, we select a reference potentiostat design and redesign this reference circuit using the gm/ID methodology in a 0.18 µm CMOS technology. Simulated results show that the power dissipation can be reduced by using the gm/ID methodology. For instance, the power dissipation of the folded cascode op-amp decreased from from 409.641 nW to 161.674 nW, indicating a 60.5% improvement. The total transistor occupation area of the folded cascode op-amp also decreased from 307 µm² to 275 µm², indicating a 10.4% improvement. We demonstrate that the gm/ID methodology is a good tool for analogue IC design as it can help the designer understand performance trade-offs as well as determine transistor dimensions, which can otherwise be very time-consuming.