一类Map-Reduce嵌入式加速器的功能虚拟样机环境

Călin Bîră, G. Stefan, M. Malita
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引用次数: 1

摘要

异构计算的出现主要是基于各种形式的并行加速器。基于Stephen Kleene提出的部分递归函数计算模型,提出了一种基于map-reduce架构的嵌入式计算加速器系列。提供了一个三层虚拟原型环境来支持嵌入式应用程序的开发。第一层是用类似lisp的函数式语言编写的。第二种是类似c的环境,它将计算的高强度部分与复杂部分分离开来。最后一个是能够为高级优化提供支持的低级模拟器。该环境是为通过调整一系列多核机器的体系结构来开发应用程序而设计的,这些机器提供了每瓦特和每平方厘米的高性能。支持我们架构方法的处理器的能源效率在标准电池28nm技术评估的10 pJ/flop范围内。
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Functional Virtual Prototyping Environment for a Family of Map-Reduce Embedded Accelerators
This emergence of the heterogeneous computing is based mainly on various forms of parallel accelerators. We present a family of accelerators for embedded computation with a map-reduce architecture based on the partial recursive functions computation model introduced by Stephen Kleene. A three-level virtual prototyping environment is provided to support the development of embedded applications. The first level is written in a Lisp-like functional language. The second is a C-like environment which segregates the intense part of the computation from the complex part. The last one is a low level simulator able to provide support for advanced optimizations. The environment is designed for developing applications by tuning the architecture of a family of many-core machines which provide high performance per Watt and cm2. The energy efficiency of processors backing our architectural approach is in the range of 10 pJ/flop evaluated for the standard cell 28nm technology.
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