Functional verification environment for I2C master controller using system verilog

Inter-Integrated Circuit (I2C) plays an important role as an interface in communication between devices. EEPROMS, ADC, DAC and RTC require an interface for communication and I2C is used as an interface between them. The RTL behavior of the I2C Master Controller is verified using System Verilog and its verification is carried out in Mentor Graphics tool. The functionality of the design is verified and there is no data loss in transmission. The proposed verification environment includes the constrained randomization, functional coverage and code coverage. In the proposed system, DUT is subjected to the verification with various coverage metrics such as code coverage, functional coverage, etc. Complex scenarios are covered with multiple cover groups which have many cover points. The code coverage obtained for the DUT is 92.38 percentage. The functional coverage for the parameters such as address and data are obtained as 100 percentage.