A. Pérez-Pascual, T. Sansaloni, J. Valls-Coquillat
{"title":"基于fpga的HIPERLAN/2基4蝴蝶","authors":"A. Pérez-Pascual, T. Sansaloni, J. Valls-Coquillat","doi":"10.1109/ISCAS.2002.1010214","DOIUrl":null,"url":null,"abstract":"This paper presents two different FPGA-implementation of radix-4 butterflies suitable for HIPERLAN 2. The two approaches lead to an efficient use of the hardware resources available in the target device and reduces the area with respect to the direct implementation of the radix-4 butterfly. Both methods reduce the area required storing the coefficients. The first one uses the symmetries of coefficients for reducing the number of functions to store; the second one takes advantage of the dual-port capability of the embedded block-RAM.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"FPGA-based radix-4 butterflies for HIPERLAN/2\",\"authors\":\"A. Pérez-Pascual, T. Sansaloni, J. Valls-Coquillat\",\"doi\":\"10.1109/ISCAS.2002.1010214\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents two different FPGA-implementation of radix-4 butterflies suitable for HIPERLAN 2. The two approaches lead to an efficient use of the hardware resources available in the target device and reduces the area with respect to the direct implementation of the radix-4 butterfly. Both methods reduce the area required storing the coefficients. The first one uses the symmetries of coefficients for reducing the number of functions to store; the second one takes advantage of the dual-port capability of the embedded block-RAM.\",\"PeriodicalId\":203750,\"journal\":{\"name\":\"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2002.1010214\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2002.1010214","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents two different FPGA-implementation of radix-4 butterflies suitable for HIPERLAN 2. The two approaches lead to an efficient use of the hardware resources available in the target device and reduces the area with respect to the direct implementation of the radix-4 butterfly. Both methods reduce the area required storing the coefficients. The first one uses the symmetries of coefficients for reducing the number of functions to store; the second one takes advantage of the dual-port capability of the embedded block-RAM.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
