{"title":"一种用于传感器网络接收机的新型ADC转换器设计","authors":"R. Laajimi, M. Masmoudi","doi":"10.1109/ICCVIA.2015.7351889","DOIUrl":null,"url":null,"abstract":"This paper describes the concept of sensor network receiver which has been made viable by a modified protocol ZIGBEE. This protocol needs a direct conversion receiver or homodyne for low manufacturing costs, easy integration and low power consumption. One of the most significant building-blocks in the homodyne architecture is Sigma-Delta Analogue to Digital Converter (ADC). We present the studying and sizing of this component which is designed to provide a higher speed of 10.24 MHz at large bandwidth of 80 MHz. For such specifications, a flexible third order ΣΔ ADC, with a mono-bit quantizer is presented and its simulations results are shown by using Matlab Simulink. With 0.35μm CMOS technology, the ΣΔ modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over a 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88 at ±1.5V supply voltage.","PeriodicalId":419122,"journal":{"name":"International Conference on Computer Vision and Image Analysis Applications","volume":"AES-23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A novel design of an ADC converter using for sensor network receiver\",\"authors\":\"R. Laajimi, M. Masmoudi\",\"doi\":\"10.1109/ICCVIA.2015.7351889\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the concept of sensor network receiver which has been made viable by a modified protocol ZIGBEE. This protocol needs a direct conversion receiver or homodyne for low manufacturing costs, easy integration and low power consumption. One of the most significant building-blocks in the homodyne architecture is Sigma-Delta Analogue to Digital Converter (ADC). We present the studying and sizing of this component which is designed to provide a higher speed of 10.24 MHz at large bandwidth of 80 MHz. For such specifications, a flexible third order ΣΔ ADC, with a mono-bit quantizer is presented and its simulations results are shown by using Matlab Simulink. With 0.35μm CMOS technology, the ΣΔ modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over a 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88 at ±1.5V supply voltage.\",\"PeriodicalId\":419122,\"journal\":{\"name\":\"International Conference on Computer Vision and Image Analysis Applications\",\"volume\":\"AES-23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Computer Vision and Image Analysis Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCVIA.2015.7351889\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Computer Vision and Image Analysis Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCVIA.2015.7351889","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel design of an ADC converter using for sensor network receiver
This paper describes the concept of sensor network receiver which has been made viable by a modified protocol ZIGBEE. This protocol needs a direct conversion receiver or homodyne for low manufacturing costs, easy integration and low power consumption. One of the most significant building-blocks in the homodyne architecture is Sigma-Delta Analogue to Digital Converter (ADC). We present the studying and sizing of this component which is designed to provide a higher speed of 10.24 MHz at large bandwidth of 80 MHz. For such specifications, a flexible third order ΣΔ ADC, with a mono-bit quantizer is presented and its simulations results are shown by using Matlab Simulink. With 0.35μm CMOS technology, the ΣΔ modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over a 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88 at ±1.5V supply voltage.