{"title":"针对SCL 180nm CMOS工艺的电流饥渴VCO设计与分析","authors":"C. Shekhar, S. Qureshi","doi":"10.1109/ises.2018.00027","DOIUrl":null,"url":null,"abstract":"This paper presents a low power 5-stage current starved voltage controlled oscillator, designed at 50 MHz. For control voltage varying from 0.4 V to 1.6 V, the oscillator frequency linearly varies from 7 MHz to 105 MHz linearly. At supply voltage of 1.8 V, the circuit is low power (134 µW) in comparison to circuits reported in the literature. It exhibits a phase noise of -101.9 dBc/Hz at 1 MHz offset from 50 MHz carrier frequency. The circuit is designed in SCL 180 nm CMOS process using cadence environment.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Design and Analysis of Current Starved VCO Targeting SCL 180 nm CMOS Process\",\"authors\":\"C. Shekhar, S. Qureshi\",\"doi\":\"10.1109/ises.2018.00027\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low power 5-stage current starved voltage controlled oscillator, designed at 50 MHz. For control voltage varying from 0.4 V to 1.6 V, the oscillator frequency linearly varies from 7 MHz to 105 MHz linearly. At supply voltage of 1.8 V, the circuit is low power (134 µW) in comparison to circuits reported in the literature. It exhibits a phase noise of -101.9 dBc/Hz at 1 MHz offset from 50 MHz carrier frequency. The circuit is designed in SCL 180 nm CMOS process using cadence environment.\",\"PeriodicalId\":447663,\"journal\":{\"name\":\"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ises.2018.00027\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ises.2018.00027","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and Analysis of Current Starved VCO Targeting SCL 180 nm CMOS Process
This paper presents a low power 5-stage current starved voltage controlled oscillator, designed at 50 MHz. For control voltage varying from 0.4 V to 1.6 V, the oscillator frequency linearly varies from 7 MHz to 105 MHz linearly. At supply voltage of 1.8 V, the circuit is low power (134 µW) in comparison to circuits reported in the literature. It exhibits a phase noise of -101.9 dBc/Hz at 1 MHz offset from 50 MHz carrier frequency. The circuit is designed in SCL 180 nm CMOS process using cadence environment.
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