Optimization of address generator hardware

This paper describes an optimization process specific to address generation hardware. By examining a set of pre-defined address sequences at both the word- and bit-levels, a pool of possible hardware solutions may be created from which a global, optimal, bit-level implementation must be found which covers all address sequences. Optimization is completed following a generally iterative method and the resulting architecture may be further improved using generic logic synthesis. The whole process has been implemented in the tool ZIPPO and results for industrially relevant examples are presented.<>