{"title":"DLX微处理器原型","authors":"B. Fagin, Pichet Chintrakulchai","doi":"10.1109/IWRSP.1992.243912","DOIUrl":null,"url":null,"abstract":"The prototyping of a functioning DLX microprocessor, based on the 32-b instruction set architecture developed by D. Patterson and J. Hennessy (in Computer Architecture: A Quantitative Approach, 1990), is described. This architecture is an emerging academic standard but has yet to be successfully prototyped. An implementation of DLX as a 12-in*15-in two-layer circuit board, containing 59 chips and running on a 2-MHz clock, is described. The execution of DLX programs and the problems encountered are discussed.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"179 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Prototyping the DLX microprocessor\",\"authors\":\"B. Fagin, Pichet Chintrakulchai\",\"doi\":\"10.1109/IWRSP.1992.243912\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The prototyping of a functioning DLX microprocessor, based on the 32-b instruction set architecture developed by D. Patterson and J. Hennessy (in Computer Architecture: A Quantitative Approach, 1990), is described. This architecture is an emerging academic standard but has yet to be successfully prototyped. An implementation of DLX as a 12-in*15-in two-layer circuit board, containing 59 chips and running on a 2-MHz clock, is described. The execution of DLX programs and the problems encountered are discussed.<<ETX>>\",\"PeriodicalId\":210681,\"journal\":{\"name\":\"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping\",\"volume\":\"179 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWRSP.1992.243912\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWRSP.1992.243912","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The prototyping of a functioning DLX microprocessor, based on the 32-b instruction set architecture developed by D. Patterson and J. Hennessy (in Computer Architecture: A Quantitative Approach, 1990), is described. This architecture is an emerging academic standard but has yet to be successfully prototyped. An implementation of DLX as a 12-in*15-in two-layer circuit board, containing 59 chips and running on a 2-MHz clock, is described. The execution of DLX programs and the problems encountered are discussed.<>
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