改进的555定时器IC只使用两个比较器

Theodora Valerie, D. Garinto, M. Alaydrus, Taufik Taufik, Eka Samsul Ma'arif
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引用次数: 0

摘要

本文提出了一种改进的555定时器集成电路,通过消除放电晶体管和SR触发器,只有两个比较器。通过利用两个比较器的互连来相互提供“设置”和“重置”条件,可以生成周期方波。仿真和实验结果表明,改进后的555定时器电路产生的时钟频率明显高于市售的555定时器电路,占空比调节更加精确和灵活。通过在所有可能的配置中替换电阻、电容和比较器规格,可以产生1MHz至89MHz频段的频率。因此,可以实现成本更低、效率更高的片上参考时钟发生器,以满足未来多用途的应用需求。
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Modified 555 Timer IC Using Only Two Comparators
This paper proposed a modified 555 timer IC with only two comparators by eliminating the discharge transistor and SR flip-flop. A periodic square waveform can be generated by utilizing the interconnection of two comparators to provide ‘Set’ and ‘Reset’ conditions to each other. The simulation and experimental results confirm that the clock frequency generated by the modified 555 timer circuit is significantly higher and duty cycle adjustment can be made more precise and flexible than the commercially available 555 timer circuit. A frequency in the band of 1MHz to 89MHz can be generated by replacing the resistors, capacitor, and comparator specification in all possible configurations. As a result, a lower cost and higher efficiency on-chip reference clock generator can be realized to fulfill versatile future application needs.
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