Power4微处理器的时钟分布

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992162

P. Restle, C. Carter, J. Eckhardt, B. Krauter, B. McCredie, K. Jenkins, A. Weger, A. Mulé

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引用次数: 72

摘要

Power4双处理器芯片上的时钟分布提供了一个关键的1.5 GHz时钟，从一个soi优化的锁相环到一个大型芯片上的15,200个引脚，具有20 ps的倾斜和35 ps的抖动。该网络包含64棵驱动单个网格的调谐树，以及无需调整电路就能按时实现目标的专用工具。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The clock distribution of the Power4 microprocessor

The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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