采用130 nm, 5LM Cu/FSG逻辑工艺的64 Mbit嵌入式FeRAM

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221194

H. McAdams, R. Acklin, T. Blake, J. Fong, D. Liu, S. Madan, T. Moise, S. Natarajan, N. Qian, Y. Qui, J. Roscher, A. Seshadri, S. Summerfelt, X. Du, J. Eliason, W. Kraus, R. Lanham, F. Li, C. Pietrzyk, J. Rickes

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引用次数: 7

摘要

一个低压(1.3V)， 64兆铁电随机存取存储器使用一个1晶体管，1电容器(1T1C)电池演示。这是迄今为止展示的最大的FRAM内存。该存储器采用最先进的130纳米晶体管和五级Cu/FSG互连工艺构建。只需要两个额外的掩模就可以将铁电模块集成到单栅极氧化物，低压逻辑过程中。该存储器的地址访问时间小于30 ns，而功耗为0.57 mW/MHz，电压为1.37 V。电池尺寸为0.54 /spl mu/m/sup 2/，电容器尺寸为0.25 /spl mu/m/sup 2/， eFRAM密度为1.13 Mb/mm/sup 2/。

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A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu/FSG logic process

A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic process. Address access time for the memory is less than 30 ns while consuming 0.57 mW/MHz at 1.37 V. An eFRAM density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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