{"title":"基于栅极工程的超结垂直IGBT电容性分析","authors":"Namrata Gupta, Alok Naugarhiya","doi":"10.1109/ICEEICT53079.2022.9768535","DOIUrl":null,"url":null,"abstract":"This paper proposed a 1.4kV-class superjunction vertical IGBT (DMG-SJIGBT) with gate workfunction variation along with stepped oxide thickness. Two distinct workfunction materials, P+ and N+ polysilicon are used as gate poly and oxide thickness is varied in x-direction. All the stepped oxide is connected via metal on the top. The proposed structure's gate oxide is narrow at the emitter and wide at the collector to improve the device performance. It has been discovered that the ON-resistance (Ron.A) of the DMG-SJIGBT has been diminished by 23% as a result of this structural modification. Gate engineering improves the transconductivity by increasing the gate-emitter capacitance (CGE) and reducing the gate-collector capacitance (CGC), which lowers switching delay. To improve performance metrics, the gate length has been optimized. A mixed mode module of SILVACO has used to perform capacitance-voltage analysis. Further the gate charge and FOM has also been measured and indicating 36% and 34% respectively reduction for proposed device signifying enhanced performance.","PeriodicalId":201910,"journal":{"name":"2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Capacitive Analysis of Superjunction Vertical IGBT with Gate Engineering\",\"authors\":\"Namrata Gupta, Alok Naugarhiya\",\"doi\":\"10.1109/ICEEICT53079.2022.9768535\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposed a 1.4kV-class superjunction vertical IGBT (DMG-SJIGBT) with gate workfunction variation along with stepped oxide thickness. Two distinct workfunction materials, P+ and N+ polysilicon are used as gate poly and oxide thickness is varied in x-direction. All the stepped oxide is connected via metal on the top. The proposed structure's gate oxide is narrow at the emitter and wide at the collector to improve the device performance. It has been discovered that the ON-resistance (Ron.A) of the DMG-SJIGBT has been diminished by 23% as a result of this structural modification. Gate engineering improves the transconductivity by increasing the gate-emitter capacitance (CGE) and reducing the gate-collector capacitance (CGC), which lowers switching delay. To improve performance metrics, the gate length has been optimized. A mixed mode module of SILVACO has used to perform capacitance-voltage analysis. Further the gate charge and FOM has also been measured and indicating 36% and 34% respectively reduction for proposed device signifying enhanced performance.\",\"PeriodicalId\":201910,\"journal\":{\"name\":\"2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-02-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEEICT53079.2022.9768535\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEEICT53079.2022.9768535","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Capacitive Analysis of Superjunction Vertical IGBT with Gate Engineering
This paper proposed a 1.4kV-class superjunction vertical IGBT (DMG-SJIGBT) with gate workfunction variation along with stepped oxide thickness. Two distinct workfunction materials, P+ and N+ polysilicon are used as gate poly and oxide thickness is varied in x-direction. All the stepped oxide is connected via metal on the top. The proposed structure's gate oxide is narrow at the emitter and wide at the collector to improve the device performance. It has been discovered that the ON-resistance (Ron.A) of the DMG-SJIGBT has been diminished by 23% as a result of this structural modification. Gate engineering improves the transconductivity by increasing the gate-emitter capacitance (CGE) and reducing the gate-collector capacitance (CGC), which lowers switching delay. To improve performance metrics, the gate length has been optimized. A mixed mode module of SILVACO has used to perform capacitance-voltage analysis. Further the gate charge and FOM has also been measured and indicating 36% and 34% respectively reduction for proposed device signifying enhanced performance.